Reverse lithographic process for semiconductor vias

Details Reverse lithographic process for semiconductor vias Reverse lithographic process for semiconductor vias

1999-06-09

2001-04-24

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S723000, C438S725000, C438S633000, C438S636000, C438S637000

Reexamination Certificate

active

06221777

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to manufacturing of submicron semiconductors and more specifically to providing more densely packed semiconductor devices.
BACKGROUND ART
An integrated circuit includes a large number of closely spaced semiconductor devices formed into and on a semiconductor substrate, typically comprising silicon. Isolation structures such as field dielectrics or shallow trench dielectrics are used to electrically isolate each individual device. A major goal in the semiconductor industry has been to reduce device size and spacing to achieve denser and denser packing.
More specifically, it has been a goal to reduce the size of memory devices such as Flash electrically erasable programmable read only memories (EEPROMs), which are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped, deeply diffused region and a more heavily doped, shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a “stacked gate” structure or word line. The stacked gate structure typically includes: a thin gate dielectric (tunnel oxide) layer formed on the surface of substrate overlying the channel region; a floating gate overlying the tunnel oxide; an interpoly dielectric overlying the floating gate; and a control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
The process of forming Flash EEPROM cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as “contacts”, must be made to connect the stack gate structures, the source regions and the drain regions to other part of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. An etch-stop layer, typically a silicon nitride material, is then formed over the entire substrate, including the stacked gate structure, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer of oxide is then deposited over the nitride layer. A layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of contact openings. An anisotropic dielectric etch is then used to etch out portions of the dielectric layer to form the gate, source and drain contact openings. The contact openings stop at the etch-stop layer. An etch-stop etch is then used to remove the etch-stop layer so that the source and drain contact openings reach the source and drain region respectively. A poly etch is then performed to etch the poly cap layer so that the gate contact openings reach the silicide layer on the stacked gate structure. The photoresist is then stripped. A conductive material, such as tungsten, is then deposited over the dielectric layer and fills the gate, source and drain contact openings to form conductive plugs. The substrate is then subjected to a chemical-mechanical polishing process which removes the conductive material above the dielectric layer.
For miniaturization, it is desirable to dispose adjacent stacked gate structures and the contacts as closely together as possible.
Individual devices are selectively interconnected after formation to other devices to achieve a desired function. One selective interconnection process for individual devices is accomplished by forming electrical channels which are connected to the contacts and to each other by connections called “vias” (the term “vias” is used collectively herein to refer to both contacts and vias). Vias are formed in desired locations through the use of conventional photolithography and etch techniques, and forming a conductive layer on the upper surface of the insulating material. The conductive layer will fill the vias and can be patterned to selectively couple specified device contacts to achieve the desired function. This process of forming a conductive layer on an insulating layer containing a plurality of vias is commonly repeated such that the device contains multiple interconnect levels and multiple inter-level dielectric layers. Multiple level interconnects enable greater functional complexity and can reduce the average length of the interconnects thereby minimizing the RC delay imposed by the interconnects.
The lateral dimension of the via is typically smaller than the lateral dimension between the stacks and of the interconnects to ensure that the via opening does not overlap on to the stacks or different interconnects. If the via opening is larger than the interconnect, the via etch process may proceed through the dielectric layer upon which the interconnect is formed. This is typically an undesirable result. Thus, as critical dimensions drop below the sub-0.25 micron region, the critical dimensions of the vias must shrink to even smaller dimensions.
The main limitation of minimum feature size, i.e., devices and vias, in a semiconductor process is the resolution of the optical lithography printing system. In an optical lithography printing system, radiation is directed from an illumination source through a patterned mask and onto a photoresist layer. The patterned mask transmits the illumination source radiation onto selected areas of the photoresist layer to reproduce the mask pattern in the photoresist layer. Resolution in optical lithography systems is limited by diffraction effects, which spread radiation from the illumination source into regions of the photoresist which are not directly exposed to the illumination source. Because of diffraction effects, it is possible to more closely control the width between lines than it is to control the size and location of vias.
The resolution of a lens depends on the wavelength of the illumination source and the numerical aperture of the lens. Rayleigh's criteria define two images as being resolvable when the intensity between them drops to 50% of the image intensity. These criteria are the 2d=0.61 lambda/NA, where 2d is the separation distance of two images, lambda is the wavelength of the energy source, and NA is the numerical aperture of the lens.
Commercially available optical photolithography machines are almost universally equipped with mercury vapor lamps as the illumination source. The characteristic energy spectrum of a mercury vapor lamp contains several distinct peaks at 365 nm, 248 nm, and 193 nm wavelengths. These peaks are commonly referred to by their industry designations. The peak associated with a wavelength of about 365 nm peak is the “I-line” and peaks at about 248 nm and 193 nm are deep ultra-violet or “DUV”.
Photolithography aligners are similarly designated such that it is common to speak of “I-line aligners” and “DUV aligners”. The DUV aligners utilizing energy having wavelengths of 248 nm and 193 nm to achieve better resolution than is achievable with I-line aligners.
As process technologies approach and surpass the resolvable limits of optical aligners, semiconductor manufacturers are forced to implement alternative photolithography techniques to achieve adequate resolution of the minimum features. Unfortunately, the conventional alternatives involve abandoning or substantially modifying the existing photolithography equipment at a prohibitive cost. Many wafer fabrication facilities, for example, have extensive capital investment in I-line aligners. To adequately resolve features in the sub-micron range, it is

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