Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-24
2010-12-07
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07849430
ABSTRACT:
A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block. The generated RDM acts as a blackbox for the identified block and is used in place of the identified block for running the timing analysis.
REFERENCES:
patent: 7181383 (2007-02-01), McGaughy et al.
patent: 7460986 (2008-12-01), Douriet et al.
patent: 7483825 (2009-01-01), Van Huben et al.
patent: 2002/0112221 (2002-08-01), Ferreri et al.
patent: 2007/0044051 (2007-02-01), McGaughy et al.
Khan Manzurul
Kwan Hang
Smith Richard W.
Dimyan Magid Y
Martine & Penilla & Gencarella LLP
Oracle America Inc.
Whitmore Stacy A
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