Reverse biasing logic circuit

Details Reverse biasing logic circuit Reverse biasing logic circuit

2002-05-21

2004-07-06

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S107000, C326S108000, C326S120000, C326S121000, C326S095000, C326S098000, C327S534000

Reexamination Certificate

active

06759873

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is integrated logic circuits. The invention finds particular use in microprocessor, ASIC, and DSP circuits.
BACKGROUND OF THE INVENTION
Power consumption and device reliability are of increasing concern in densely integrated circuits and systems, such as those used with portable electronics. In particular, as the power supply voltage in CMOS systems is continually scaled down to less than one volt for newer integrated circuit applications, performance degradation of the integrated circuits within these CMOS systems occurs. CMOS systems experience performance degradation because of reduced gate to source transistor voltages (V
GS
) in the integrated circuit as well as an increase of the standby current due to scaled threshold voltages (V
t
) of the integrated circuit transistors.
Various circuit techniques have been proposed to overcome performance degradation as well as other problems caused by reduced supply voltages in a sub-threshold region below 1V being fed to the integrated circuits of CMOS systems. More specifically, MOS parameters such as threshold voltages, gate voltages, and source voltages of the integrated circuit transistors have been controlled to reduce performance degradation. While these methods have overcome some of the performance degradation problems, each of these methods has drawbacks when implemented in a sub-threshold region.
The methods implementing threshold voltage control use MOS transistors with different threshold voltages. These methods improve performance by employing low V
t
transistors in the active mode of the integrated circuit, and employing high V
t
transistors in the standby mode to reduce standby leakage current. Such methods directed to MOS threshold voltage control were addressed by S. M. Muto et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold-Voltage CMOS,” IEEE (Pub. No. 30 (8): 847-854).
FIG. 1
shows a multi-threshold CMOS circuit design suggested by S. M. Muto et al. and is generally designated
4
. The circuit
4
provides a plurality of transistors
6
with different threshold voltages. Improved performance during active mode of the circuit
4
is accomplished by using low V
t
transistors and a low threshold voltage NAND gate
8
. Leakage current is reduced during standby mode by using high V
t
transistors (Q
1
, Q
2
). A drawback of using this type of circuit design, however, is that large transistor sizes for Q
1
and Q
2
are required to meet performance requirements in the sub-threshold region. Moreover, since the virtual power lines (VDDV, GNDV) float in standby mode, a special data holding circuit is required to preserve data safely.
Other known threshold voltage control methods vary the substrate bias voltages to control V
t
. In these methods, different substrate bias voltages are applied by a self substrate bias generator to provide a low V
t
while the integrated circuit is in an active mode and a high V
t
while the circuit is in a standby mode. These methods, however, also have drawbacks. Some methods require a large voltage to change V
t
by a few hundred mV since V
t
is proportional to the square root of the transistor source to substrate voltage. Other methods have problems due to the need for a triple well structure and/or power lines for well bias. Moreover, in some methods there is generally a slow response time to well bias change. Further, other substrate bias control methods employing dynamic V
t
according to an input state have also been found to be unsatisfactory because of an increased leakage electric current loss due to the inherent forward bias electric current of pn-junctions.
Gate control voltage methods propose reducing the leakage current flowing through the power source transistor Q
1
of
FIG. 1
by using an on-chip boost voltage for the control signal (SL). These methods provide control signal voltages that enable transistor Q
1
to be reverse biased in the standby mode to suppress the leakage electric current. A drawback of using such methods is that they need N-well separation and a high efficient on-chip boost voltage generator to perform, which is difficult to achieve in the sub-threshold region. Oxide reliability, as well as lost logic state information while the circuit is in the standby mode are further drawbacks to using these methods, especially since additional circuitry is required for holding data. Source voltage control schemes also incur some of the drawbacks discussed herein related to a limitation of the low supply voltage, requirement of a complicated data holding scheme and/or on-chip boost voltage generator, and gate oxide reliability.
SUMMARY OF THE INVENTION
A reverse biasing circuit is provided which limits standby leakage electric current losses by reverse biasing transistors during a standby mode of a logic function sub-circuit of the reverse biasing circuit. The logic function circuit includes one or more logic transistors, and receives an input which is processed to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that enables the logic function circuit to switch between an active mode and a standby mode. In the standby mode, a gate to source biasing of the power source transistor causes reverse biasing of the power source transistor and at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the logic function circuit.


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