Reverse-biased P/N wells isolating a CMOS inductor from the...

Details Reverse-biased P/N wells isolating a CMOS inductor from the... Reverse-biased P/N wells isolating a CMOS inductor from the...

2006-06-06

2006-06-06

Tran, Minh-Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S531000

Reexamination Certificate

active

07057241

ABSTRACT:
A double well structure beneath an inductor to isolate it from the substrate. Contacts are provided for the deeper well and the substrate, to reverse bias the junction between the substrate and the deep well. In one embodiment, for a P-substrate, the deep well is an N-well, and the other well is a P-well. Both the N-well junction with the substrate, and the junction between the N-well and the P-well are reverse biased. This improves the quality factor of the inductor structure above the wells by reducing eddy currents. In one embodiment, the P-well is striped. The deeper N-well extends upward into the gaps between the stripes. The stripes will further reduce the amount of eddy current by adding a reverse biased sidewall junction to the eddy current path, further helping to increase the quality factor of the inductor.

REFERENCES:
patent: 6060752 (2000-05-01), Williams
patent: 6441442 (2002-08-01), Wong
patent: 2002/0179977 (2002-12-01), Wong et al.

Affiliated with

Also associated with

Rating

Reverse-biased P/N wells isolating a CMOS inductor from the... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reverse-biased P/N wells isolating a CMOS inductor from the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reverse-biased P/N wells isolating a CMOS inductor from the... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3709923