Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1998-07-13
2001-02-13
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030
Reexamination Certificate
active
06188617
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a redundancy circuit for semiconductor memories having word lines organized in segments. When a word line is defective in a segment, a redundant word line in the same or in a different segment can be activated by virtue of inter-segment redundancy by a segment select signal and through fuse sets assigned to the respective segments.
The word lines of semiconductor memories are usually organized in segments. If so-called inter-segment redundancy is provided, it is possible, given the occurrence of a defective word line, to use redundant word lines both from the same segment in which the defective word line is present and from neighboring segments in order to replace the defective word line.
A problem that arises in the case of inter-segment redundancy is that, if appropriate, the activation of the segment with the defective word line is intended to be prevented and, instead of this, the segment in which the redundant word line is located is intended to be activated. Possibly, this may also be the segment with the defective word line if that segment additionally contains the redundant word line.
In order not to lose any access time, the decoding of the signal which selects the segment to be activated, that is to say the decoding of the segment select signal, must take place very rapidly in such a redundancy circuit for semiconductor memories.
To date, segment select signals which specify the segment with the redundant word line have been generated in existing redundancy circuits by evaluating fuse output signals with the aid of the original row addresses. In other words, an additional logic stage is necessary here in order logically to combine the fuse output signal with the address information.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a redundancy circuit for semiconductor memories, which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type and which permits segment select signals to be generated, given the occurrence of defective word lines, without such an additional logic stage.
With the foregoing and other objects in view there is provided, in accordance with the invention, a redundancy circuit in a semiconductor memory with word lines organized in segments. The redundancy circuit provides for inter-segment redundancy for selecting a redundant word line upon an occurrence of a defective word line in one of the segments of the semiconductor memory, wherein the redundant word line is selected from the segment containing the defective word line or from a different segment. The improvement comprises: a plurality of fuse sets assigned to respective segments of the semiconductor memory, and a device connected to the fuse sets for evaluating the fuse set output signals and issuing segment select signals activating the redundant word line in the segment containing the defective word line or in the different segment based on the fuse set output signals thus evaluated.
In accordance with a concomitant feature of the invention, there is provided a circuit connected to receive the fuse set output signals from the fuse sets. In the event of a correspondence between an applied row address and a fused address of the fuse set assigned to a given segment, the circuit activates a signal which is assigned to an address of the given segment, overwrites the segment select signal generated from the row address, and activates the redundant word line.
In other words, the above-noted objects are satisfied by the fact that the segment select signal can be generated by evaluating the output signal of the fuse sets. Specifically, if a correspondence is determined between an applied row address and the fused address of the fuse set assigned to a segment, a circuit connected downstream of the fuse sets activates a signal which is assigned to the address of that segment and overwrites a segment select signal generated from the row address and activates the redundant word line.
The redundancy circuit according to the invention thus converts the output signals of the fuse sets directly, that is to say without the assistance of row addresses, into segment select signals. As a result, logic combination of the fuse output signals with the address information is unnecessary and a logic stage is obviated. Consequently, access time is not increased in spite of the flexible inter-segment redundancy, and the segment to be activated can be decoded very rapidly by means of the segment select signal generated directly from the fuse output signal.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a redundancy circuit for semiconductor memories, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.
REFERENCES:
patent: 5359560 (1994-10-01), Suh
patent: 5459690 (1995-10-01), Rieger
patent: 0 442 319 A2 (1991-08-01), None
patent: 0 554 901 A2 (1993-08-01), None
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
Zarabian A.
LandOfFree
Reundancy circuit for semiconductor memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reundancy circuit for semiconductor memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reundancy circuit for semiconductor memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2593274