Retry-based late race resolution mechanism for a computer...

Details Retry-based late race resolution mechanism for a computer... Retry-based late race resolution mechanism for a computer...

2005-05-17

2005-05-17

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S147000, C709S213000

Reexamination Certificate

active

06895476

ABSTRACT:
A retry-based mechanism resolves late race conditions in a computer system between a first processor writing modified data back to main memory and a second processor trying to obtain a copy of the modified data. A low occupancy cache coherency protocol tracks ownership and sharing status of memory blocks. When a memory reference operation forwarded from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, the first processor issues a Retry command to the second processor. In response to the Retry command, the second processor issues another memory reference operation. This time, however, the operation explicitly specifies the version of the memory block being written back to main memory. Once the memory block has been written back to main memory, thereby providing main memory with the desired version, a copy is sent to the second processor.

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