Retrieving data blocks with reduced linear addresses

Details Retrieving data blocks with reduced linear addresses Retrieving data blocks with reduced linear addresses

2003-12-23

2008-10-28

Ellis, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S118000

Reexamination Certificate

active

07444457

ABSTRACT:
Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.

REFERENCES:
patent: 6161166 (2000-12-01), Doing et al.
Main et al., Data Structures and Other Objects Using C++, Aug. 1998, Addison Wesley, pp. 544-560.

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