Retiming circuits using a cut-based approach

Details Retiming circuits using a cut-based approach Retiming circuits using a cut-based approach

2007-04-10

2007-04-10

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10504217

ABSTRACT:
Methods and apparatus for retiming an integrated circuit are described. According to certain embodiments, the retiming comprises performing a timing analysis for one or more paths in the integrated circuit to obtain slack values, selecting one of the paths based on the slack values obtained, and determining a retimeable cut along the path selected. The retimeable cut in these exemplary embodiments comprises a set of input pins for one or more logic instances in the integrated circuit to which one or more retimed sequential elements can be coupled in order to improve the slack value of the path selected. In particular embodiments, the retimeable cut is automatically selected from multiple possible cuts along the path selected. Other embodiments for retiming integrated circuits are disclosed, as well as integrated circuits and circuit design databases retimed by the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.

REFERENCES:
patent: 5751593 (1998-05-01), Pullela et al.
patent: 7000137 (2006-02-01), Sivaraman et al.
patent: 7010763 (2006-03-01), Hathaway et al.
patent: 2002/0023252 (2002-02-01), Lee et al.
Deokar et al., “A Fresh Look at Retiming via Clock Skew Optimization,”Proceedings of the 32nd DAC, 5 pgs (1995).
Fishburn, “Clock Skew Optimization,”IEEE Trans. on Computers, vol. 39, No. 7, pp. 945-951 (Jul. 1990).
Leiserson et al., “Optimizing Synchronous Circuitry,”J. VLSI and Computer Systems, pp. 41-67 (1983).
Liu et al., “Maximizing Performance by Retiming and Clock Skew Scheduling,”Proceedings of the 36th DAC, pp. 231-236 (1999).
Malik et al., “Retiming and Re-synthesis: Optimizing Sequential Networks with Combinational Techniques,”IEEE Trans. on CAD, vol. 10, No. 1, pp. 74-84 (Jan. 1991).
Pan, “Performance-driven Integration of Retiming and Resynthesis,”Proceedings of the 36th DAC, pp. 243-246 (1999).
Shenoy et al., “Efficient Implementation of Retiming,”IEEE Intl. Conf. on CAD, pp. 226-233 (1994).
Singh et al., “Integrated Retiming and Placement for Field Programmable Gate Arrays,”FPGA '2002, pp. 67-76 (2002).
Suaris et al., “Smart Move: A Placement-aware Retiming and Replication Method for Field Programmable Gate Arrays,”Proc. ASICON'2003, Beijing, China, pp. 67-70 (2003).
Cong et al., “FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,”IEEE Trans. on Computer-Aided Design, vol. 13, No. 1, pp. 1-12 (Jan. 1994).

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