Reticle for wafer test structure areas

Details Reticle for wafer test structure areas Reticle for wafer test structure areas

2011-08-23

2011-08-23

Chambliss, Alonzo (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S724000, C257S786000, C438S018000, C438S129000

Reexamination Certificate

active

08003984

ABSTRACT:
Techniques are provided for forming die on wafers with large area test structures between primary die. A reticle is used to pattern each die. The pattern on the reticle forms a primary die and test structures in scribelines that abut edges of the die. A reticle can be used to form additional test structures that are separated from the primary die. A gap is formed between the additional test structures and the primary die in each exposure. In subsequent exposures, test structures for adjacent die are formed in the gaps between the previously formed primary die and their additional test structures. These techniques are used to provide larger test structure area between each primary die. A blade can be used to block portions of the reticle that form the additional test structures. The reticle can then be used to pattern die with smaller test structures during high volume chip production.

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