Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-08-08
2004-11-02
Clark, S. V. (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000
Reexamination Certificate
active
06812129
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to semiconductor fabrication. More particularly, the present invention relates to a photolithographic device adapted to protect electrical contact portions of a wafer-in-process, as well as an intermediate wafer product created during a dual damascene process.
BACKGROUND
In the manufacture of integrated circuits (ICs), microlithographic techniques are used to pattern one or more layers of conductive circuitry on a wafer. Referring to the wafer
10
shown in
FIGS. 1-2
, one typical microlithography patterning technique is a dual damascene process, which begins with the formation of openings
19
in a first dielectric material structure
18
. A conductive material is then deposited over the dielectric structure
18
and within the openings
19
. A chemical mechanical polish (CMP) is used to ablate the conductive material from a top surface of the dielectric structure, leaving plugs of conductive material
20
within the openings
19
.
A hard mask layer
14
and a second dielectric material structure
12
are respectively positioned over the first dielectric structure
18
. Vias
16
are formed in the second dielectric structure
12
and the hard mask layer
14
, the vias
16
extending to the conductive plugs
20
. A photoresist material is then deposited over the second dielectric structure
12
and within the vias
16
. With a photolithographic device, such as a semiconductor mask or a reticle, the photoresist material is exposed and then developed. Specifically, the wafer-in-process is etched to create a large open area. The remaining photoresist is then removed, and a conductive material
62
is deposited within the vias
16
and over the dielectric structure. A CMP of the conductive material may be performed to prepare the wafer
10
for further processing. The wafer
10
thus formed may be incorporated within a semiconductor device, such as a memory cell in a DRAM.
A disadvantage in the above-described method is that all of the photoresist material in the vias
16
is exposed and developed. This uncovers the electrical contact portions adjacent to the hard mask layer
14
(i.e., the conductive plugs
20
) during the subsequent etching of the wafer-in-process to create the large open area. This may lead to possible damage of the hard mask layer
14
and/or the conductive plugs
20
.
While seen in the fabrication of all wafers, this disadvantage is more prevalent when large circuitry is to be formed, such as in a large metal bus or a large bonding pad. Using a conventional photolithographic device for developing the photoresist material in wafers, the depth of focus (DOF) of the radiant energy is greater than the depths of the vias
16
, and hence all the photoresist material within the vias
16
may be exposed and developed, or removed.
There exists a need for a photolithographic device which protects the electrical contacts of wafers-in-process during subsequent wafer fabrication processes.
SUMMARY
An embodiment of the present invention provides a photolithographic device adapted for developing a portion of photoresist material on a wafer-in-process including vias within a dielectric layer overlain by the photoresist material. The device includes a radiant energy transparent portion and radiant energy blocking portions. The blocking portions are registered to the wafer-in-process to prevent direct radiant energy transmission to the photoresist material directly overlaying the vias.
Another embodiment of the present invention provides a system for fabricating a wafer including a source of radiant energy and a photolithographic device positioned between the source of radiant energy and a wafer-in-process including vias within a dielectric layer overlain with a photoresist material. The photolithographic device has a radiant energy transparent portion and radiant energy blocking portions. The blocking portions are registered to the wafer-in-process to prevent direct radiant to energy transmission to the photoresist material directly overlaying the vias.
Another embodiment provides a method of fabricating a wafer including a plurality of conductive plugs in a first dielectric layer overlain by a hard mask layer and a second dielectric layer. The method includes forming vias in the second dielectric layer, each via extending to a corresponding conductive plug, applying a photoresist material to fill the vias and cover the second dielectric layer, and exposing a portion of the photoresist material so as to leave unexposed a second portion of the photoresist material located at a lower portion of the vias. The exposing includes using a photolithographic device which is adapted to prevent direct transmission of radiant energy to the photoresist material directly overlaying the vias.
Another embodiment provides a wafer-in-process including a first dielectric layer, at least one conductive plug within said first dielectric layer, a hard mask layer positioned atop said first dielectric layer, a second dielectric layer over said hard mask layer, at least one via extending through said second dielectric layer and said hard mask layer to said conductive plug, and photoresist material positioned only at a portion of said via adjacent said hard mask layer
The foregoing and other objects, features and advantages of the invention will be more readily understood from the following detailed description of preferred embodiments of the invention, which is provided in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
is a top view of part of a portion of a wafer constructed in accordance with an embodiment of the present invention.
FIG. 2
is a cross-sectional view taken along line II—II of FIG.
1
.
FIG. 3
is a top view of a photolithographic device constructed in accordance with an embodiment of the present invention.
FIG. 4
is a cross-sectional view of the photolithographic device of PIG.
3
is use to form the wafer of FIG.
1
.
FIG. 5
is another cross-sectional view of the formation of the wafer of the
FIG. 1
,
2
, and
4
.
FIGS. 6A-L
are a flow diagram illustrating the wafer fabrication process depicted in
FIGS. 1
,
2
,
4
and
5
.
FIG. 7
is a flow diagram illustrating the wafer fabrication process depicted in
FIGS. 1
,
2
and
4
-
6
.
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Clark S. V.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
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