Retaining ring interconnect used for 3-D stacking

Details Retaining ring interconnect used for 3-D stacking Retaining ring interconnect used for 3-D stacking

2001-09-20

2003-06-03

Paladini, Albert W. (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S261000

Reexamination Certificate

active

06573461

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to chip stacks, and more particularly to a 3-D chip stack with a retaining ring interconnect.
As is currently known in the art, packaged components are often stacked using a variety of approaches. In all of the approaches to date, the concept has been for the end user to mount the stacks on the surface of a solid board such as a printed circuit board (PCB). More particularly, one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two to as many as eight memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., a chip stack) which is mountable to the “footprint” typically used for a single packaged device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the 3-D stacking process, a solder bridge is typically applied to interconnect neighboring layers or PCB substrates that carry IC devices. However, in the ever changing world of electronics, smaller, faster, and more functionality are always requested. Shrinkage of devices generally results in more I/O's in a smaller package. Design rules are requiring shorter signal paths to accommodate the faster die speeds. With the tighter pitches becoming more prominent in the packages, solder bridging between neighboring interconnects becomes more difficult to control. This forces the issue of eliminating solder paste because of its limitation on density. Another concern relates to environmental issues with the lead content in solder and the concern of the disposal. A method to resolve these problems is required.
SUMMARY OF THE INVENTION
The invention provides a retaining ring interconnection to replace the solder joints between neighboring substrates or layers for stacking IC devices, such that the limitation in density and environmental problems caused by lead content attendant to the use of solder paste are eliminated.
A PCB substrate is provided with conductive pads on two opposing surfaces thereof. The two conductive pads are electrically connected with each other by a via through the PCB substrate. A retaining ring is plated on the peripheral portion of at least one of the conductive pads. When the PCB substrate is stacked with the other PCB substrate with the same structure, the retaining rings of two PCB substrates are aligned and faced with each other. A conductive paste is applied between two aligned retaining rings, and an adhesive is applied between two adjoining surfaces of the two PCB substrates. By a lamination process, a eutectic bond is formed of the conductive paste between the retaining rings of two adjoining pads of the two PCB substrates. Meanwhile, the adhesive tightly bonds the two adjoining surfaces of the two PCB boards.


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