Restricted scan reordering technique to enhance delay fault...

Details Restricted scan reordering technique to enhance delay fault... Restricted scan reordering technique to enhance delay fault...

2007-03-06

2007-03-06

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10892022

ABSTRACT:
Disclosed is a method and apparatus for improved delay fault testing by optimizing the order of scan cells in a scan chain. The order of the scan cells is determined by using a cost value for an order of scan cells, the cost value being computed from costs assigned to orderings of individual pairs of scan cells. These costs can be based on the number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain. The disclosed techniques allow for enhanced delay fault coverage by rearranging scan flip-flops without increasing routing overhead.

REFERENCES:
patent: 6148425 (2000-11-01), Bhawmik et al.
patent: 2004/0015803 (2004-01-01), Huang et al.
Cheng, K-T et al., “A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits”, International Test Conference 1991.
Dervisoglu, B.I. et al., “Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement”, International Test Conference 1991.
Patil, S. et al., “Skewed-Load Transition Test: Part II, Coverage”, International Test Conference 1992.
Wang, S. et al., “A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs”, ITC International Test Conference 2003.
Mao, W. et al., “Reducing Correlation to Improve Coverage of Delay Faults in Scan-Path Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 5, May 1994.
Savir, J., “At-Speed Test is Not Necessarily an AC Test”, International Test Conference 1991.

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