Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-05-01
2002-03-19
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S194000
Reexamination Certificate
active
06359816
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a device for measuring the response time of a circuit and to a method of measuring the response time of a circuit.
BACKGROUND OF THE INVENTION
More particularly, but not exclusively the invention relates to a method of determining the response time of a deeply embedded memory, for example a static RAM and to a device for determining the response time of a deeply embedded memory, for example a static RAM.
Current techniques for evaluating embedded fast SRAM designs use either extremely high performance testing devices, which are costly or alternatively require physical access to internal nodes. The latter tends to be inaccurate and is not capable of providing statistical sampling over long periods of time.
It will be desirable to provide a method and device capable of providing statistical data on different circuit examples and to use conventional test apparatus to collect statistically significant data.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a device for measuring the response time of a circuit, the circuit having an output for providing a response to a stimulus at an input node thereof, the device comprising first circuitry having a clock node and an output, said first circuitry being connected to store at an output thereof an output condition, said output condition corresponding to a state of said circuit output at the time of occurrence of a clock pulse at said clock node, the device further comprising second circuitry and third circuitry, said second circuitry being responsive to a second circuitry input signal at its input to provide said stimulus at said input node of said circuit, and said third circuitry being responsive to a third circuitry input signal at its input to provide a clock pulse at said clock node of said first circuitry whereby said response time is determined by a time delay between said second circuitry input signal and said third circuitry input signal, and further comprising connecting circuitry disposed between said outputs of said second and third circuitry, and said circuit input and said clock node, wherein said connecting circuitry is operable alternatively to connect said second circuitry output to said circuit input and said third circuitry output to said clock node, or said second circuitry output to said clock node and said third circuitry output node to said circuit output.
Advantageously the first circuitry comprises flip-flop circuitry.
Preferably said delay between said second and third circuitry input signals corresponds to a delay which causes said output condition to be a desired output condition.
Preferably said desired output condition is a just valid condition such that a decreased delay results in an invalid condition.
According to a second aspect of the present invention there is provided a device for measuring a response time of a circuit between an input node and a circuit output thereof, wherein said circuit output is connected via first connecting circuitry to an output pad, said device comprising a first timing signal source for providing a first timing signal to said input node via a first path, clocked circuitry having a clock node and being connected at said circuit output, said clocked circuitry having an output to said first connecting circuitry, said clocked circuitry being responsive to a clock signal at said clock node to provide to said first connecting circuitry a signal existing at said circuit output immediately prior to the occurrence of said clock signal, the device further comprising a second timing signal source for providing a second timing signal as said clock signal to said clock node via a second path, and means for determining a delay between said first and second timing signals, and further comprising controllable connecting circuitry disposed at inputs to said first and second paths and connected to said first and second timing signal sources, said controllable connecting circuitry having a control input for selectively connecting said first timing signal source to said first path and said second timing signal source to said second path, or said first timing signal source to said second path and said second timing signal source to said first path.
Preferably said delay between said first and second timing signals corresponds to a delay which causes a desired condition at said output pad.
Preferably said desired condition is a just valid condition such that a decreased delay results in an invalid condition.
Conveniently said controllable connecting circuitry comprises a multiplexer.
Advantageously said clocked circuitry comprises a flip-flop.
Preferably the device further comprises a sensing device connected to said output pad for sensing a desired output thereat.
Preferably again said circuit comprises a static RAM.
Conveniently said static RAM comprises address latch circuitry having a latch clock node as said input node, an array of memory cells coupled to said address latch circuitry, and sense amplifier circuitry having a sense amplifier output node as said output node.
According to a further aspect of the present invention there is provided a method of measuring the response time of a circuit having a circuit output for providing an output in response to a stimulus applied to a circuit input, the method comprising:
providing second circuitry having a clock node, said second circuitry having an output for storing an output condition, said output condition corresponding to the state of said circuit output at the time of occurrence of a clock pulse at said clock node;
providing switching circuitry having inputs coupled to first and second input pads via a first and third circuitry, output coupled to said circuit input and said clock node;
controlling said switching circuitry to connect said first input pad to said circuit input, and said second input pad to said clock node;
successively applying a first timing signal to said first input pad whereby a said stimulus is applied to said circuit input, and at a variable first delay after each application, providing a second timing signal to said second input pad; whereby a clock pulse is applied to said clock node;
determining, a value of said variable first delay corresponding to a desired output condition of said second circuitry;
controlling said switching circuitry to connect said first input pad to said clock node and said second input pad to said circuit input;
successively applying a third timing signal to said second input pad whereby a said stimulus is applied to said circuit input, and at a variable second delay after each application providing a fourth timing signal to said first input pad, whereby a clock pulse is applied to said clock node;
determining a value of said variable second delay corresponding to said desired output condition of said second circuitry; and
averaging said value of said variable first delay and said value of said variable second delay to provide said response time.
Preferably said second circuitry comprises flip-flop circuitry.
REFERENCES:
patent: 4736351 (1988-04-01), Oliver
patent: 5440516 (1995-08-01), Slemmer
patent: 5537663 (1996-07-01), Belmont et al.
patent: 5809227 (1998-09-01), Basile
patent: 5875135 (1999-02-01), Patwardhan et al.
patent: 6185637 (2001-02-01), Strongin et al.
patent: 39 10507 (1990-10-01), None
patent: 0 343 537 (1989-11-01), None
Mai Son
Morris James H.
STMicroelectronics Limited
Wolf Greenfield & Sacks P.C.
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