Resource interconnection patterns in a customized memory...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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C709S220000, C710S300000

Reexamination Certificate

active

06889275

ABSTRACT:
A system and method are provided that include determining optimum memory organization in an electronic device, wherein further determined are optimum resource interconnection patterns. One aspect of the system and method includes determining resource, e.g., memories and data paths, interconnection patterns of complex bus structures with switches using system-level information about the data-transfer conflicts. The quantity of memories within an electronic device, the size of the memories and the interconnection between the memories, including the interconnection of the memories with one or more data paths, defines a memory organization of an electronic device. Another aspect of the system and method relates to selecting an optimized memory organization, including selecting an optimized interconnection pattern between the memories and between the memories and the data paths.

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“Performance modeling of the interconnect structure of a three-dimensional integrated RISC processor/cache system” by Kuhn S.A.; Kleiner, M.B.; Ramm, P.; Weber, W. (abstract only) Publication Date: Nov. 1996*
F. Catthoor et al., ‘Custom Memory Management Methodology’, Kluwer Ac. Publ., 1998, Table of Contents and pp. 193-300.

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