Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2006-11-28
2006-11-28
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S112000, C326S093000
Reexamination Certificate
active
07142020
ABSTRACT:
A method and apparatus for operating logic circuitry with recycled energy. Logic circuitry is used which has a node for storing energy and a return node that is connected to energy storage circuitry. The logic circuitry operates, using energy stored on the node, to determine a logic output based on a logic input during a first phase. The energy storage circuitry capture a portion of the stored energy during the operation of the logic circuitry and transfers a portion of the captured energy back to the node during a second phase. The energy storage circuitry oscillates with a determinable period and is tunable so that its oscillations can be synchronized to a clock.
REFERENCES:
patent: 3651334 (1972-03-01), Thompson et al.
patent: 4562365 (1985-12-01), Redfield et al.
patent: 4570085 (1986-02-01), Redfield
patent: 4599528 (1986-07-01), Redfield
patent: 5559478 (1996-09-01), Athas et al.
patent: 6028454 (2000-02-01), Elmasry et al.
patent: 6208170 (2001-03-01), Iwaki et al.
patent: 6246266 (2001-06-01), Bosshart
patent: 6255853 (2001-07-01), Houston
patent: 0 626 757 (1994-11-01), None
patent: 63-093223 (1988-04-01), None
Athas et al., “Low-Power Digital Systems Based on Adiabatic-Switching Principals,”IEEE Transactions on Very Large Scale Integration(VLSI)Systems, vol. 2, No. 4, Dec. 1994, pp. 398-409.
Tzartzanis et al., “Design and Analysis of a Low-Power Energy-Recovery Adder,”IEEE, 1995, pp. 66-69.
W. Athas et al., “AC-1: a clock-powered microprocessor,”Proceedings of the 1997 International Symposium on Low Power Electronics and Design, Aug. 18-20, 1997, Islped '97. ACM Press. pp. 328-333.
Chun-Keung Lo & Philip C. H. Chan, “An Adiabatic Differential Logic for Low-Power Digital Systems, ” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, Issue 9, Sep. 1999, pp. 1245-1250.
Guo Weiwei
Wu Jianbin
Yao Yuan
Dechert LLP
Diepenbrock III Anthony B.
Le Don
PicoNetics, Inc.
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