Resonant clock and interconnect architecture for digital...

Details Resonant clock and interconnect architecture for digital... Resonant clock and interconnect architecture for digital...

2011-07-05

2011-07-05

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S291000

Reexamination Certificate

active

07973565

ABSTRACT:
A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).

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