Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2000-07-07
2002-03-12
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S185030, C257S209000
Reexamination Certificate
active
06356496
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to electronic devices and, more specifically, to a resistor fuse and methods of manufacturing and operating the resistor fuse.
BACKGROUND OF THE INVENTION
While technological advances are permitting an increasing number of circuit elements (e.g., transistors, resistors) to be incorporated into an integrated circuit, reducing or eliminating defects in the circuit elements is becoming increasingly more difficult as the size of the circuit elements are reduced. The reduced size brings about an increased susceptibility to defects caused by material impurities and tolerances in the fabrication process of such integrated circuits.
Improved testing procedures generally allow the defects to be identified upon completion of the integrated circuit. Circuits containing a large number of defective circuit elements are usually discarded. Those containing only a small number of defective circuit elements, however, may be preserved, for example, by substituting non-defective redundant circuit elements for the defective ones, thereby significantly reducing the number of rejected integrated circuits. Additionally, many integrated circuits are generally constructed with a number of redundant circuit elements and semiconductor fuses arranged such that a redundant circuit element may be readily substituted for a defective one by merely opening the appropriate fuses.
Currently, semiconductor devices with fuses employ metal fuses. The metal fuses, however, may be difficult to program, since it may require as much as 200 mA to open the metal fuse. Further, it may be difficult to ascertain whether a particular metal fuse has actually opened, since the metal fuse may merely experience a change in resistance. Detection schemes for use with the metal fuses are necessarily more complex than a simple open circuit/short circuit detection scheme. Additionally, since the metal fuses are constructed at the metal level (e.g., a metal three level), an alternative is needed when using processes such as copper damascene technology since the copper in the fuse will diffuse throughout the semiconductor integrated circuit if the fuse is opened (i.e., blown).
Accordingly, what is needed in the art is a resistor fuse that overcomes the deficiencies of the prior art metal fuses.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides, in one aspect, a resistor fuse for use in a semiconductor device having an operating voltage. In one embodiment, the resistor fuse includes a silicon layer located over a semiconductor wafer and a metal silicide layer located over the silicon layer. The resistor fuse has a predetermined current threshold and is configured to open if a current through the resistor fuse at the operating voltage exceeds the current threshold.
The present invention therefore provides, in this aspect, a resistor fuse formed from a silicon layer and a metal silicide layer. The resistor fuse of the present invention thus avoids the use of a metal layer as was commonly employed in prior art fuses. The resistor fuse of the present invention may, therefore, be used even when employing processes including, for instance, copper damascene technology.
Another aspect of the present invention provides a method of forming the resistor fuse. The method includes forming a silicon layer over a semiconductor wafer. A metal layer is then deposited over the silicon layer. The metal layer is thermally treated to form a metal silicide layer over the silicon layer.
Yet another aspect of the present invention provides a method of operating a resistor fuse in a semiconductor device having an operating voltage. The method includes applying a voltage within the operating voltage across the resistor fuse. A current is developed through the resistor fuse, which may cause the resistor fuse to open depending on the voltage applied across the resistor fuse.
Another aspect of the present invention provides a method of trimming an adjustable resistor. The adjustable resistor includes a first resistor fuse having a first resistance. The adjustable resistor further includes a second resistor fuse, having a second resistance different from the first resistance, coupled in parallel to the first resistor fuse. The method includes applying a voltage across the adjustable resistor. First and second currents are then developed through the first and second resistor fuses, respectively. At least one of the first and second resistor fuses may open as a function of the voltage applied across the adjustable resistor. A total resistance of the adjustable resistor may thus be trimmed using the foregoing method.
Still another aspect of the present invention provides a method of programming a non-volatile multi-state memory cell. The memory cell includes a first resistor fuse having a first resistance. The memory cell further includes a second resistor fuse, having a second resistance different from the first resistance, coupled in parallel with the first resistor fuse. The memory cell still further includes a third resistor fuse, having a third resistance different from the first and second resistances, coupled in parallel with the first and second resistor fuses. The method includes applying a voltage across the memory cell. First, second and third currents are developed through the first, second and third resistor fuses, respectively. The currents cause any number of the first, second and third resistor fuses to selectively open as a function of the voltage. The memory cell may thus attain a state as a function of the first, second and third resistances.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5068696 (1991-11-01), Yang et al.
patent: 5099148 (1992-03-01), McClure et al.
patent: 5872734 (1999-02-01), Chan et al.
patent: 5882998 (1999-03-01), Sur, Jr. et al.
patent: 5912839 (1999-06-01), Ovshinsky et al.
patent: 5976943 (1999-11-01), Manley et al.
patent: 6222244 (2001-04-01), Arndt et al.
“A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process” by Mohsen Alavi, Mark Bohr, Jeff Hicks, Martin Denham, Allen Cassens, Dave Douglas and Min-Chun Tsai: 1997 IEEE; pp. 855-858.
IBM Technical Disclosure Bulletin: vol. 26, No. 8: Jan. 1984: entitled “Element Trimming Fusible Link” by D. J. Nickel.
“Programming Mechanism of Polysilicon Resistor Fuses” by David W. Greve: Apr. 1982: pp. 20-25.
Carroll Michael Scott
Hui Frank Yauchee
Ivanov Tony G.
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