Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-20
2001-10-16
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S903000, C257S904000, C438S381000, C438S382000, C438S384000
Reexamination Certificate
active
06303965
ABSTRACT:
TECHNICAL FIELD
This invention relates to formation of resistors, to formation of static random access memory (SRAM) circuitry, and to integrated circuitry.
BACKGROUND OF THE INVENTION
This invention arose from challenges associated with fabrication of resistors for SRAM circuitry and will be described relative to SRAM circuitry. However, the invention will have applicability to other circuitry, as the artisan will appreciate, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine Of Equivalents.
An SRAM cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. The different output voltages correspond to a binary stored “1” or a “0”. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable voltage differential between the two nodes of the cell. The polarity of this voltage difference is sensed by external circuitry to determine the operating state of the memory cell. The two possible output voltages produced by a static memory cell are determined by the upper and lower circuit supply voltages. Intermediate output voltages may occur transiently during performance of the SRAM cell.
The operation of a static memory cell is in contrast to other types of memory cells, such as DRAM cells, which do not have stable operating states. A DRAM cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods.
FIG. 1
shows an example prior art SRAM cell
350
such as is typically used in high-density static random access memories. Static memory cell
350
comprises n-channel pulldown (driver) transistors
380
and
382
having drains respectively connected to load resistors
384
and
386
. Transistors
380
and
382
are typically metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate.
The source regions of transistors
380
and
382
are tied to a low reference or circuit supply voltage, labeled V
ss
which is typically referred to as “ground.” Resistors
384
and
386
are respectively connected in series between a high reference or circuit supply voltage, labeled V
cc
, and the drains of the corresponding transistors
380
and
382
. The drain of transistor
382
is connected to the gate of transistor
380
by a line
376
, and the drain of transistor
380
is connected to the gate of transistor
382
by a line
374
to form flip-flop having a pair of complementary two-state outputs.
A memory flip-flop, such as that described above in connection with
FIG. 1
, forms one memory element of an integrated array of static memory elements. A pair of access transistors, such as access transistors
390
and
392
, are provided to selectively address and access individual memory elements within the array. Access transistor
390
has one active terminal connected to the drain of transistor
380
. Access transistor
392
has one active terminal connected to the drain of transistor
382
. A plurality of complementary column line pairs, such as the single pair of complementary column lines
352
and
354
as shown, are connected to the remaining active terminals of access transistors
390
and
392
, respectively. A row line
356
is connected to the gates of access transistors
390
and
392
.
Reading static memory cell
350
requires activating row line
356
to connect outputs
368
and
372
to column lines
352
and
354
. Writing to static memory cell
350
requires first placing selected complementary logic voltages on column lines
352
and
354
, and then activating row line
356
to connect those logic voltages to outputs
368
and
372
. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
Resistors
384
and
386
are commonly fabricated from highly resistive forms of polysilicon. It would be desirable to provide alternative resistor constructions.
SUMMARY OF THE INVENTION
The invention encompasses resistors comprising a thin layer of dielectric material and methods of forming such resistors. The invention also encompasses integrated circuitry comprising such resistors, including SRAM circuitry, and encompasses methods of forming such integrated circuitry.
REFERENCES:
patent: 4609903 (1986-09-01), Toyokura et al.
patent: 5049970 (1991-09-01), Tanaka et al.
patent: 5093706 (1992-03-01), Mitsuhashi et al.
patent: 5140299 (1992-08-01), Andrews, Jr. et al.
patent: 5200356 (1993-04-01), Tanaka
Shubat, A., et al., “A Bipolar Load CMOS SRAM Cell for Embedded Applications”,IEEEvol. 16, No. 5, May 1995; pp. 169-171.
Okumura, T., et al., “A SiOxResistor Load SRAM Process for ASIC Applications”, 1988; pp. 25.6.1-25.6.4.
Flynn Nathan
Micro)n Technology, Inc.
Quinto Kevin
Wells, St. John, Roberts Gregory & Matkin P.S.
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