Resistless methods of gate formation in MOS devices

Details Resistless methods of gate formation in MOS devices Resistless methods of gate formation in MOS devices

1997-01-02

1998-11-03

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438592, 438655, 438656, 438657, 438669, H01L 2128

Patent

active

058308016

ABSTRACT:
A method of forming an MOS gate includes providing a silicon substrate having a gate oxide formed thereon, forming a polysilicon layer on the gate oxide, defining a gate area including forming an oxide mask by positioning a light mask adjacent a surface of the polysilicon layer and exposing the surface through the light mask to a deep ultra violet light in an ambient containing oxygen. A layer of metal is deposited and annealed to form a silicide only where the layer of metal and polysilicon layer are in contact. The remaining metal layer and mask are removed, using the silicide as a mask, wherein the remaining polysilicon and the silicide form an MOS gate. Sidewall spacers are formed on opposing sides of the MOS gate and used in forming self aligned source and drain regions.

REFERENCES:
patent: 5460693 (1995-10-01), Moslehi
patent: 5543356 (1996-08-01), Murakami et al.
patent: 5618760 (1997-04-01), Soh et al.

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