Resistive memory

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S158000

Reexamination Certificate

active

08036015

ABSTRACT:
A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier.

REFERENCES:
patent: 6707710 (2004-03-01), Holden
patent: 6721198 (2004-04-01), Kang
patent: 6781873 (2004-08-01), Ishikawa et al.
patent: 6809976 (2004-10-01), Ooishi
patent: 6853599 (2005-02-01), Oh et al.
patent: 6982908 (2006-01-01), Cho
patent: 7221585 (2007-05-01), Bessho
patent: 7813166 (2010-10-01), Jung et al.
patent: 2002/0154531 (2002-10-01), Lowrey et al.
patent: 2004/0047216 (2004-03-01), Ishikawa et al.
patent: 2008/0002483 (2008-01-01), Rinerson et al.
patent: 2008/0158936 (2008-07-01), Bertin et al.
patent: 2008/0310241 (2008-12-01), Sakoh
patent: 2008/0315335 (2008-12-01), Ueda
patent: 2004-103060 (2004-04-01), None
Background Art Information.
U.S. Appl. No. 12/543,793, filed Oct. 26, 2004, Ooishi.

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