Resistive gate FET flip-flop storage cell

Static information storage and retrieval – Systems using particular element – Semiconductive

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365174, 365184, G11C 1140

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active

RE0320714

ABSTRACT:
An improved bistable FET circuit is disclosed which employs a reduced number of device elements and occupies less space in an integrated circuit. The flip-flop circuit includes the FET device having its source connected to a first potential and a second FET device having its source also connected to the first potential. The first FET device has a gate electrode composed of a resistive material with the first side connected to the drain of the second FET device and the second side connected to a second potential. The second FET device has a gate electrode comprised of a resistive material with the first side connected to the drain of the first FET device and a second side connected to the second potential. In this manner, the resistive gate of the first device serves as the load for the second device and the resistive gate of the second device serves as the load for the first device. Application of this circuit to electrically programmable PLA's and to random access memories is disclosed.

REFERENCES:
patent: 3714522 (1973-01-01), Komiya et al.
patent: 3943286 (1976-03-01), Tsurushima
patent: 4025940 (1977-05-01), Kimura et al.
patent: 4092735 (1978-05-01), McElroy
patent: 4157557 (1979-06-01), Sato et al.
IEEE Transactions on Electron Devices "A Resistive-Gated IGFET Tetrode" by C. Hu et al., Jul. 1971, pp. 418-425.

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