Resistive cross point array of short-tolerant memory cells

Details Resistive cross point array of short-tolerant memory cells Resistive cross point array of short-tolerant memory cells

2001-06-22

2003-10-14

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S209000

Reexamination Certificate

active

06633497

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to data storage devices. More specifically, the present invention relates to a data storage device including a resistive cross point array of memory cells.
A typical Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells, word lines extending along rows of the memory cells, and bit lines extending along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
The memory cells may include spin dependent tunneling (“SDT”) junctions. The magnetization of an SDT junction assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of ‘0’ and ‘1.’ The magnetization orientation, in turn, affects the resistance of the SDT junction. The resistance of the SDT junction is a first value if the magnetization orientation is parallel and a second value if the magnetization orientation is anti-parallel.
The logic state of an SDT junction may be read by sensing the resistance state of the SDT junction. However, in some architectural configurations, the memory cells in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the memory cell at that cross point in parallel with resistances of memory cells in the other rows and columns. In this regard, the array of memory cells may be characterized as a cross point resistor network.
A typical SDT junction has a tunneling barrier that is only a few atoms thick. Controlling the fabrication process to produce such thin barriers for an entire array of memory cells is difficult. It is possible that some of the barriers will be thinner than designed and contain structural defects. If certain SDT junctions have tunneling barriers that are defective or thinner than designed, those SDT junctions might be shorted.
If one SDT junction is shorted, the shorted SDT junction will be unusable. In a resistive cross point array that does not use switches or diodes to isolate memory cells from one another, the other memory cells in the same column and row will also be rendered unusable. Thus, a single shorted SDT junction memory cell can cause a column-wide error and a row-wide error.
Error code correction could be used to recover data from a complete column or row of unusable memory cells. However, correcting a thousand or more bits in a single column or row is costly, both from a time standpoint and a computational standpoint. Moreover, a typical storage device might have more than one column and row with a shorted SDT junction.
There is a need to overcome the problems associated with shorted SDT junctions in resistive cross point memory arrays that do not use isolation devices such as diodes and transistors.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a data storage device includes a resistive cross point array of memory cells. Each memory cell includes a memory element and an electrically conductive hard mask material on the memory element. The hard mask material functions as a resistive element in series with the memory element. If a memory element becomes shorted, the shorted memory element will cause only a randomized bit error. However, the hard mask prevents the shorted memory element from causing column-wide and row-wide errors.


REFERENCES:
patent: 5861328 (1999-01-01), Tehrani et al.
patent: 5981297 (1999-11-01), Baselt
patent: 6055178 (2000-04-01), Naji
patent: 6331944 (2001-12-01), Monsma et al.
patent: 2001/0024380 (2001-09-01), Goebel et al.
U.S.S.N. 09/663,752 filed Sep. 15, 2000 and entitled “Short-tolerant resistive cross point array” (Attorney docket PDNO 10001383-1).

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