Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2000-05-26
2001-12-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000
Reexamination Certificate
active
06329836
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing high speed output drivers that incorporate resistive series termination and pre-distortion functions.
In order to enable high speed communication, a transmitter with a high speed output driver is needed. For communication over distances appreciable with respect to the signal bit period, termination is also needed to prevent unwanted reflections that would corrupt the signal. Transmission line termination can be implemented outside of the transmitter integrated circuit. This, however, increases the external components count and the cost of the product. It is, therefore, preferred to provide a self-terminating resistive output driver that incorporates the termination. It is also desirable to eliminate or minimize inter-symbol interference (ISI) which results from a frequency bandlimited system. Pre-distortion is a useful technique which allows the transmitter to use its output driver to cancel ISI. Further, in order to keep the output driver inexpensive, it is also desirable to be able to implement the driver in conventional digital CMOS technology.
Accordingly, there is a need for a high-speed output driver circuit that operates at the highest speed possible in a digital CMOS technology, incorporates within its circuit resistive termination and pre-distortion to cancel ISI.
SUMMARY OF THE INVENTION
The present invention offers method and circuitry for implementing high speed output drivers that are self-terminating and incorporate pre-distortion to cancel ISI. Broadly, in one embodiment, an output driver according to the present invention includes multiple resistive drive elements that are pulse-activated in succession to synthesize an output waveform which behaves similar to a single resistive drive element responding to the a non-bandlimited input signal. Due to bandwidth limitation of the pre-drive circuit, it is not possible to generate a single pre-drive signal without introducing significant ISI into the pre-drive signal. By arraying and activating the resistive driver and pre-driver circuits according to the present invention, each individual pre-driver can be equilibrated before each pulse, and any bandwidth limiting of the pulse is seen similarly for each bit period so that ISI does not result.
In a specific embodiment, field effect transistors operating in triode region implement the resistive drive elements. In one embodiment, the final output driver impedance is controlled by modifying the high voltage generated by the pre-driver that pulse activates an output driver leg. In an alternate embodiment, the pre-driver always generates pulses which have the digital power supply voltage, but instead different numbers of output driver legs are pulse activated for a given bit period. The parallel combined resistance is then controlled by digitally selecting different numbers of output drivers to pulse activate for a given bit period. The present invention accomplishes pre-distortion while still maintaining a constant termination output driver impedance by keeping the total number of output driver legs that are turned on for a given bit period constant, while instead selecting some number of legs to connect to the rail corresponding to the opposite bit value.
Accordingly, in one embodiment, the present invention provides an output driver circuit connected to drive an output terminal, including a plurality of resistive elements selectively activated to drive the output terminal; and a timing circuit coupled to the plurality of resistive element, and configured to generate a sequence of activation signals to activate the plurality of resistive elements, wherein, in response to the sequence of activation signals, the plurality of resistive elements are activated in succession to drive a respective plurality of consecutively occurring data bits onto the output terminal.
In another embodiment, the present invention provides a method of driving an output terminal comprising selectively coupling N resistive elements to the output terminal, where N is a positive integer; and sequentially activating the N resistive elements to drive a corresponding sequence of N data bits onto the output terminal.
In yet another embodiment, the present invention provides an output driver circuit for driving an output terminal, comprising: N pull-up transistors coupled between the output terminal and a logic high power supply, the N pull-up transistor operating in linear region when turned on; N pull-down transistors coupled between the output terminal and a logic low power supply, the N pull-down transistors operating in linear region when turned on; N pull-up pre-drivers respectively coupled to the N pull-transistors, and coupled to receive timing control signals and data bits carrying logic high information; and N pull-down pre-drivers respectively coupled to the N pull-down transistors, and coupled to receive timing control signals and data bits carrying logic low information, wherein, N is a positive integer, and wherein, in response to activation signals generated by respective pre-drivers, each one of the N pull-up or pull-down transistors is turned on in succession to drive N consecutive data bits onto the output terminal, respectively.
A better understanding of the nature and advantages of the high speed output driver of the present invention may be gained with reference to the following description and the accompanying drawings.
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Bosnyak Robert J.
Drost Robert J.
Cho James H
Sun Microsystems Inc.
Tokar Michael
Townsend and Townsend / and Crew LLP
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