Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2011-03-15
2011-03-15
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060
Reexamination Certificate
active
07907467
ABSTRACT:
A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.
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Cho Woo-Yeong
Kang Sang-Beom
Oh Hyung-Rok
Park Joon-min
F. Chau & Associates LLC
Nguyen Tuan T.
Samsung Electronics Co,. Ltd.
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