Resist protect oxide structure of sub-micron salicide process

Details Resist protect oxide structure of sub-micron salicide process Resist protect oxide structure of sub-micron salicide process

2002-09-13

2004-11-09

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S299000, C438S300000, C438S763000, C438S950000

Reexamination Certificate

active

06815274

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a Resist Protect Oxide (RPO) structure while avoiding conventional problems of having to apply a time-consuming wet oxide etch, which typically leads to the occurrence of oxide voids and to the occurrence of metal residue inside the oxide voids.
(2) Description of the Prior Art
Improvements in the performance of semiconductor devices are achieved by continuing reductions in semiconductor devices and device feature dimensions. A major class of semiconductor devices comprises CMOS devices, the creation of CMOS devices is well known in the art. The continued miniaturization of devices and device features leads to a continued reduction in the thickness of the various layers of semiconductor material that are used for the creation of semiconductor devices.
During the formation of CMOS devices over the surface of a substrate, devices of different polarities, such as PMOS and NMOS devices, can be created overlying the surface of one substrate and as part of a continuing processing stream. Also, some of these different devices may be processed following a different processing stream. For instance, some of the CMOS devices may by provided with salicided, low resistivity points of contact to the gate electrodes of the CMOS devices. Other CMOS devices that are also created over the surface of the same substrate are not provided with salicided points of electrical contact to the CMOS devices. For this reason, that is the difference in processing steps for the creation of different CMOS devices over the surface of one substrate, some of these devices are coated with a layer of Resistance Protective Oxide (RPO).
As an example of the difference in processing of CMOS devices that are created over the surface of one substrate can be cited the creation of self-aligned contact points to the source/drain regions and the gate electrode of a CMOS device. By universally covering all CMOS devices that are created over the surface of the substrate with a layer of RPO after the gate structures, including the gate spacers, have been created, the devices can be divided into devices that need to be provided with salicided points of electrical contact and those that do not. By then covering the devices that do not need to be provided with salicided points of contact with a patterned layer of RPO that covers these devices, the layer of RPO can be removed from the devices which need to be provided with salicide points of electrical contact, thus exposing the surfaces that need to be salicided and enabling the completion of the salicidation for the devices that are not covered by a layer of Resistance Protective Oxide.
With the continuing decrease in device feature size, the thickness of the layer of RPO is also further reduced, which places increased demands on the quality of the layer of RPO that is deposited. The quality of the layer of RPO is typically evaluated using parameters such as Field-to-Breakdown (V
bd
) and Charge-to-Breakdown (Q
bd
). One of the problems that is encountered in the era of sub-micron device feature size is the occurrence of voids in the interface between the layer of RPO and the layer of polysilicon that is used for the creation of the gate structure. It is critical that the occurrence of such voids is prevented, the invention provides such a method by controlling the quality of the layer of RPO that is used.
U.S. Pat No. 6,348,389 B1 (Chou et al.) shows a method for forming and etching a RPO layer.
U.S. Pat. No. 6,319,784 B1 (Yu et al.) shows a salicide process with an RPO layer comprising a dielectric material such as oxide, nitride or SiON.
U.S. Pat. No. 6,015,730 (Wang et al.) reveals an RPO layer process.
U.S. Pat. No. 6,037,222 (Huang et al.) shows a RPO layer.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method for the creation of a RPO layer that avoids the creation of voids between the layer of RPO and an underlying layer of polysilicon.
Another objective of the invention is to provide a method for the creation of a RPO layer that does not lead to the presence of metal residue in voids between the layer of RPO and an underlying layer of polysilicon.
Yet another objective of the invention is to provide a method for the creation of an RPO layer of adequate thickness so that the created layer of RPO provides protection to non-salicided surfaces.
A still further objective of the invention is to provide a method for the creation of a RPO layer that takes advantage of a good wet stop of each layer and that provides an improved and wider RPO etch processing window.
A still further objective of the invention is to provide a method for the creation of a RPO layer that uses full wet etch processing only.
In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO). A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned upper or first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower or second layer of silicon dioxide, completing the patterning of the layer of RPO.


REFERENCES:
patent: 6015730 (2000-01-01), Wang et al.
patent: 6037222 (2000-03-01), Huang et al.
patent: 6130168 (2000-10-01), Chu et al.
patent: 6319784 (2001-11-01), Yu et al.
patent: 6348389 (2002-02-01), Chou et al.
patent: 2002/0132430 (2002-09-01), Willer et al.

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