Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
1999-11-10
2001-07-24
Williams, Alexander O. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S791000, C257S787000, C257S781000, C257S789000, C257S778000, C257S737000, C257S790000
Reexamination Certificate
active
06265784
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a resin sealed semiconductor device in which an LSI chip is connected to a wiring substrate. More particularly, this invention relates to a resin sealed semiconductor device having a bare chip package configuration.
So-called “bare chip package” type semiconductor devices according to the prior art have a construction in which an LSI chip is connected to a wiring substrate by metal bumps, or the like. These semiconductor devices are not free from the problem that a thermal strain develops in the metal bumps due to the difference of coefficients of linear thermal expansion between the LSI chip resulting in the wiring substrate, and the metal bumps undergoing fatigue failure. In order to solve this problem, in a known measure, a gap portion between the LSI chip and the wiring substrate is charged with an epoxy type thermosetting resin containing fine particles such as glass particles (generally called “fillers”). With this arrangement, thermal deformation between the LSI chip and the wiring substrate is restricted so that the thermal stress occurring in the metal bumps can be reduced and connection reliability of the metal bumps can be improved.
Such a measure will be explained by taking JP-A-7-66326 by way of example. This prior art reference illustrates a schematic sectional view of a semiconductor device that is produced by packing a resin at peripheral portions of solder bumps that electrically connect a semiconductor chip such as an LSI chip to a glass substrate. This reference proposes to improve connection reliability of the solder bumps by charging the resin into the gap portion between the semiconductor chip and the glass substrate thereby mitigating deformation resulting from the difference of the coefficients of thermal expansion between the semiconductor chip and the glass substrate.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a resin sealed semiconductor device that can prevent breakage resulting from a thermal stress, is economical, and has high reliability.
It is another object of the present invention to provide a resin sealed semiconductor device that can prevent an erroneous operation of a semiconductor integrated circuit resulting from visible rays.
A lower fabrication cost of semiconductor devices has been required nowadays in addition to their higher performance. Ceramic type substrate materials typified by the glass substrate described above or alumina have a high material cost and a high production cost. If an LSI chip is mounted to an organic resin wiring substrate that is more economical than the ceramic materials, semiconductor devices will be supplied more economically.
When the LSI chip is mounted directly to the organic resin wiring substrate, however, the following problem develops. The difference of coefficients of thermal expansion between an organic resin and silicon as the material of the LSI chip is greater than that between a ceramic substrate and silicon. Therefore, even when a sealing resin is charged in the manner described above, thermal stress acting on the solder bumps, or the like, will increase and will accelerate fatigue failure of the solder bumps. As the difference of coefficients of linear thermal expansion increases, overall thermal deformation of the semiconductor device becomes greater with the result that a large thermal stress occurs in the sealing resin that restricts the thermal deformation, and cracks and peeling will occur in the sealing resin and in the interface of the LSI chip and the wiring substrate, respectively.
When an LSI chip is mounted in a bare chip package, the LSI chip is exposed outside. Therefore, the semiconductor integrated circuit inside the LSI chip is likely to operate erroneously in some cases due to the influences of light. In any event, when the LSI chip is directly mounted on the organic resin material, reliability of the semiconductor device may drop.
In a resin sealed semiconductor device in which the LSI chip is mounted on the organic resin material, therefore, the present invention contemplates to improve thermal fatigue failure life of the solder bumps through optimization of the mechanical properties of the sealing resin. The present invention optimizes also a fillet shape of the sealing resin in order to restrict the cracks inside the sealing resin and restrict interfacial breakage, even when the LSI chip is mounted in the bare chip package form to not only the organic resin wiring substrate but also to the ceramic wiring substrate. In this way, the present invention accomplishes a high reliability resin sealed semiconductor device that improves connection reliability of the solder bumps.
Among the problems described above, the problem of the fatigue failure of the solder bumps can be solved when a sealing resin is selected having mechanical properties capable of reducing the strain that occurs in the metal bumps such as the solder bumps and governs their fatigue life.
The sealing resin in the present invention has a feature in that its modulus of longitudinal elasticity E (MPa) satisfies the relation 3,430≦E≦16,000, and its coefficient of linear thermal expansion &agr; (ppm/° C.) satisfies the following expression (5):
&agr;
1
(
E
)≦&agr;(
E
)≦&agr;
2
(
E
) (5)
where:
&agr;
1
(
E
)=6.24×10
−8
E
2
−1.38×10
−3
E
+26.8 (6)
&agr;
2
(
E
)=2.28×10
−7
E
2
−5.69×10
−3
E
+93.6 (7)
3,430≦
E
≦16,000 (8)
FIG. 1
shows a relational graph of these expressions (5) to (8). The hatched portion in
FIG. 1
represents the mechanical properties of the sealing resin according to the present invention.
Next, the problem of the cracks inside the sealing resin and the interfacial peeling of the LSI chip, the wiring substrate, and so forth, can be solved by optimizing the fillet shape of the sealing resin.
When the sealing resin has a fillet shape that extends from the side surface of the LSI chip in a curved shape and reaches the wiring substrate, the fillet shape needs to satisfy the following relation:
S<H≦S+C
(9)
where:
S: height of gap between LSI chip and wiring substrate (mm),
H: height of fillet (mm),
C: thickness of LSI chip (mm), and
L: length of fillet leg.
H=L
(10)
FIG. 2
is a schematic sectional view of the fillet shape of the sealing resin. It is a feature of the present invention that the fillet of the sealing resin hangs on the side surface of the LSI chip, and the range of the fillet height is from the lower end to the upper end of the side surface of the LSI chip.
Next, the problem of erroneous operation of the semiconductor integrated circuit resulting from visible rays can be solved when the sealing resin is colored in black lest the visible rays transmit through the sealing resin.
FIG. 3
is a schematic sectional view showing the resin sealed semiconductor device sealed by the sealing resin that is colored in black.
FIG. 4
is a schematic sectional view of a resin sealed semiconductor device the sealing resin of which is colored in black into a depth of 200 &mgr;m from its surface. It is another feature of the present invention that the sealing resin is colored in black lest the visible rays transmit through the sealing resin. It is sufficient if the sealing resin is colored in black to a depth of at least 200 &mgr;m from the surface.
The resin sealed semiconductor device according to the present invention optimizes, and selects suitably, the modulus of longitudinal elasticity and the coefficient of linear thermal expansion of the sealing resin for reducing the strain of the metal bumps such as the solder bumps. The present invention thus improves precisely the fatigue failure of the metal bumps. The resin sealed semiconductor device of the present invention optimizes also the fillet shape of the sealing resin, restricts the cracks occurring inside the sealing resin and the interfacial peeling with the LSI chip, a
Doi Hiroaki
Kawano Kenya
Miura Hideo
Yasukawa Akio
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Williams Alexander O.
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