Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
2003-03-21
2004-08-10
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S789000, C257S782000, C257S783000, C257S787000
Reexamination Certificate
active
06774501
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2000-297834, P2000-297835, P2000-311047, P2000-311048, P2000-311049, P2000-311051, filed on Sep. 29, 2000; the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a resin-sealed semiconductor device excellent in heat cycle resistance and mountability in which warpage deformation of a semiconductor chip is suppressed, and, particularly, relates to a resin-sealed semiconductor device using a copper lead frame and a die bonding material and an encapsulating material used therein.
2. Description of the Related Art
A semiconductor chip such as a LSI circuit is electrically joined with a lead frame and sealed by a encapsulating material for the purpose of protection from an external environment, thus taking the form of a package. Representative examples of the package include a dual inline package (DIP). The DIP is a pin-insertion type, which attaches a semiconductor device by inserting pins into a mounting substrate. Recently, due to requirements for miniaturization and higher functionality of an electronic itself in addition to high integration and higher speed of the LSI circuit, higher density mounting has been increasingly carried out. Therefore, in addition to the pin-insertion type package such as the DIP, a surface-mount package has come to be mainly used in high pin count application.
Representative examples of the surface-mount type package include a quad flat package (QFP). The QFP is designed to be directly fixed to a surface of the mounting substrate with solder or the like. The QFP has an advantage in that the package can be mounted on both sides of the mounting substrate, additionally, the package can be made thin to reduce an occupied space.
As shown in
FIG. 1A
, in the QFP, on a die bond pad
15
located at substantially center of the lead frame, a semiconductor chip
11
is mounted with a die bonding material
12
interposed therebetween. The chip
11
and a lead
16
are electrically connected with gold wires
14
. The entire resultant structure is sealed with an encapsulating material
13
to be formed into a package (resin-sealed semiconductor device)
10
. The package is then solder-mounted on a printed circuit board (not shown) to be used.
Problems in the process of manufacturing such a package, and in the subsequent mounting and usage phases are: a warpage of a chip after curing of the die bonding material, which is caused when the chip
11
is fixed to the pad
15
, as shown in
FIG. 1B
, and a crack
17
and separation
18
a
and
18
b
within the package caused by high temperature reflow or a beat cycle in the mounting and usage phases, as shown in FIG.
1
C.
The warpage of the chip in the package manufacturing process is caused by thermal stress due to a difference in physical property between the semiconductor chip
11
and the lead frame (die bond pad)
15
. Particularly, in the case of using a lead frame of copper (Cu), the difference in coefficient of thermal expansion between the lead frame and the semiconductor chip is large, and warpage may be easily caused in the semiconductor chip
11
. In the worst case, the semiconductor chip itself is broken. When the semiconductor chip
11
bonded to the lead frame is conveyed with warpage remaining through a rack, a jam is caused in conveying, and further a wiring error is caused in the subsequent step.
In the following mounting and usage phases, the package
10
is exposed to high temperature in reflowing when the package
10
is solder-mounted on a motherboard. In infrared reflow equipment or the like generally used for solder mounting, the semiconductor device is heated to up to 215-245° C. at highest. In the solder mounting, tin-lead eutectic solder was widely used. However, recently, since lead adversely affects the environment, lead-free solder, not using lead, has been increasingly developed. The lead-free solder generally has a higher melting point than that of the tin-lead eutectic solder. Accordingly, the semiconductor chip is heated up to 245-280° C. in solder mounting. In this reflow step, the adhesive force of the encapsulating material
13
to an inner lead
16
a
or the die bond pad
15
is lowered because of the thermal stress due to the heating and moisture absorption of the encapsulating material
13
. When the adhesive force is lowered, the separation
18
a
is caused in an interface between the inner lead
16
a
and the encapsulating material
13
, or the separation
18
b
is caused in an interface between the die bond pad
15
and the encapsulating material
13
. The adhesion of copper to the encapsulating material after being subjected to the thermal history is severely lowered. In the case of using the copper lead frame, the effect thereof is serious.
FIG. 2
is an enlarged view showing the separation and the crack shown in FIG.
1
C. As shown in
FIG. 2A
, when the semiconductor device is subjected to heat shock by repeated heat cycles in actual use, the crack
17
is caused in the encapsulating material
13
starting from an edge of the die bond pad
15
. Such a crack is caused by thermal stress due to a difference in physical property among the component materials of the package. In the worst case, the crack may reach the surface of the resin-sealed semiconductor device. When the crack reaches the surface of the package, water goes through the crack, and moisture resistance reliability is lowered. As shown in
FIG. 2B
, the separation
18
a
between the inner lead
16
a
and the encapsulating material
13
causes a crack
19
in the gold wire
14
by the heat cycles subsequently repeated during use, and in the worst case, breaking of the wire may occur. On the other hand, the separation
18
b
between the die bond pad
15
and the encapsulating material
13
causes a crack
17
extending from a corner of the die bond pad
15
by the subsequent heat cycle.
As a countermeasure against the above-described problems, the following methods and the like have been proposed and implemented for the purpose of suppressing the reduction of the adhesive force due to the moisture absorption. In one method, the semiconductor device itself is packed in moisture-proof packing, and the package is opened just before surface mounting onto the motherboard for use. In another method, the semiconductor device is dried at 100° C. for 24 hours just before surface mounting, and then the solder mounting is carried out.
However, such preprocessing methods have problems in that they require a longer manufacturing process and take time and effort. The present invention is to solve these problems, and an object of the present invention is to provide a resin-sealed semiconductor device which overcomes the defects of the conventional QFP. The resin-sealed semiconductor device can reduce the warpage of the semiconductor chip after curing the die bonding material even in the case of using the Cu lead frame, and increase reliability of the connection between the inner lead and the die bond pad during solder mounting. Furthermore, the resin-sealed semiconductor device can suppress the crack starting from the edge of the die bond pad in the heat cycles.
SUMMARY OF THE INVENTION
In order to achieve the above-described object, one aspect of the present invention provides a resin-sealed semiconductor device, which includes a lead frame including a die bond pad and an inner lead, a semiconductor chip placed on the die bond pad with a die bonding material interposed therebetween, and a encapsulating material encapsulating the semiconductor chip and the lead frame, and properties of the die bonding material and the encapsulating material satisfy a certain relation. When a flexural strength of the encapsulating material at 25° C. is &sgr;b; a shear strain energy of the encapsulating material against the inner lead at a peak temperature during solder mounting is Ui; and a shear strain e
Kawasumi Masao
Kawata Tatsuo
Kurafuchi Kazuhiko
Sakai Hiroyuki
Suzuki Naoya
Flynn Nathan J.
Hitachi Chemical Co. Ltd.
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