Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
2000-03-24
2003-06-03
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S737000, C257S738000, C257S784000, C257S786000, C257S787000, C257S693000, C257S678000, C257S780000, C257S774000
Reexamination Certificate
active
06573612
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. HEI11-216109 filed on Jul. 30, 1999, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a resin-encapsulated semiconductor device and a process for fabricating the same. More particularly, it relates to a resin-encapsulated semiconductor device of a ball grid array (BGA) type which is called a chip size package (CSP), and a process for fabricating the same.
2. Related Art
Conventionally, resin-encapsulated semiconductor devices of the BGA type called CSP as shown in FIG.
9
(
c
) have been widely utilized.
The resin-encapsulated semiconductor device comprises a wiring substrate
25
for mounting a semiconductor chip which includes thereon a patterned wiring
26
, a plurality of first through holes
31
for external connection and a plurality of lands
27
for external connection which cover the entire openings of the first through holes
31
and partially constitute the patterned wiring
26
, and a semiconductor chip
21
mounted thereon. The semiconductor chip
21
is electrically connected to the patterned wiring
26
through wire bonding using an Au wire
23
. The semiconductor chip
21
and the Au wire
23
are encapsulated with a resin
22
for encapsulation. Further, external terminals
24
for external connection are mounted on a surface opposite to a chip-mounting surface of the wiring substrate
25
and electrically connected to the semiconductor chip
21
via the lands
27
.
The resin-encapsulated semiconductor device is fabricated by the following process.
First, the first through holes
31
for mounting the external terminals are formed in an area array matrix of the wiring substrate
25
.
On a surface of the wiring substrate
25
where the semiconductor chips
21
are to be mounted, the patterned wiring
26
and the lands
27
for external connection are formed of a conductive film, and marks
30
representative of cutting lines are formed of the conductive film in the periphery of the wiring substrate
25
. The lands
27
partially serve as the patterned wiring
26
and cover the respective first through holes
31
.
Then, the semiconductor chips
21
are mounted on the wiring substrate
25
and electrically connected to the patterned wiring
26
formed on the wiring substrate
25
through wire bonding using Au wires
23
.
The semiconductor chips
21
arranged on the wiring substrate
25
and the Au wires
23
are all encapsulated in one-piece with the resin
22
by a transfer mold technique.
Then, the encapsulated semiconductor chips
21
are divided into individual chips. At this time, as shown in FIG.
9
(
a
), a surface of the wiring substrate
25
where the external terminals are to be mounted is adhered to a jig
33
for fixing the wiring substrate. The chip-mounting surface of the wiring substrate
25
is faced upward so that the marks
30
of cutting lines can be observed from the chip-mounting surface side of the wiring substrate
25
. The cutting line is defined by joining a pair of marks
30
formed on the opposite sides of the periphery of the wiring substrate
25
. The resin
22
and the underlying wiring substrate
25
are cut and divided with a single cutting blade
29
along the cutting line in one operation as shown in FIG.
9
(
b
).
Thereafter, as shown in FIG.
9
(
c
), the external terminals
24
are mounted at the first through holes
31
from the external terminal mounting surface and subjected to a reflow process to metallically bond the external terminals
24
and the patterned wiring
26
or the lands
27
. Thus, an end product is obtained.
In the above-described fabrication process, the semiconductor chips
21
encapsulated with the resin
22
on the wiring substrate
25
are divided into individual chips
21
by cutting. That is, the wiring substrate
25
and the resin
22
formed of different materials are cut in one operation with one cutting blade
29
. Therefore, the cutting blade
29
is extremely worn out.
Further, since cut faces of the resin
22
and the wiring substrate
25
are in the same plane, the resin encapsulant
22
and the wiring substrate
25
may be separated from each other at an interface therebetween.
SUMMARY OF THE INVENTION
The present invention provides with a process for fabricating a resin-encapsulated semiconductor device comprising the steps of: (a) forming a plurality of first through holes for external connection in a substrate for mounting semiconductor chips; (b) forming a conductive film on a chip-mounting surface of the substrate and patterning the conductive film into a plurality of patterned wirings and a plurality of lands which cover the entire openings of the first through holes and partially constitute the patterned wirings; (c) mounting two or more semiconductor chips on the chip-mounting surface of the substrate; (d) mounting external connection terminals at the first through holes from a terminal-mounting surface opposite to the chip-mounting surface and connecting the semiconductor chips to the external terminals through the lands; (e) encapsulating the two or more semiconductor chips in one-piece with a resin encapsulant; (f) cutting the substrate with a first cutting blade from the terminal-mounting surface of the substrate; (g) cutting the resin encapsulant with a second cutting blade thinner than the first cutting blade; and (h) dividing the resulting substrate for the individual semiconductor chips.
Further, the present invention provides with a resin-encapsulated semiconductor device comprising; a substrate for mounting a semiconductor chip including thereon a patterned wiring, a plurality of first through holes for external connection and a plurality of lands which cover the entire openings of the first through holes and partially constitute the patterned wiring, a semiconductor chip mounted on the substrate, the semiconductor chip being encapsulated with a resin, and terminals for external connection being mounted on a surface opposite to a chip-mounting surface of the substrate and electrically connected to the semiconductor chip through the lands, wherein an edge of the substrate is positioned inside an edge of the resin for encapsulation.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
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Satoshi Takabayashi et al., Technical Report of IEICE, CPM98-166, 1998-12, “FBGA/CSP flexible assembly lines with whole-cavity . . . ”, pp. 59-65.
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Williams Alexander O.
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