Resin-encapsulated semiconductor device

Details Resin-encapsulated semiconductor device Resin-encapsulated semiconductor device

2000-09-18

2003-08-26

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S222000, C257S686000

Reexamination Certificate

active

06611063

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a resin-encapsulated semiconductor device and, more particularly to the structure of the resin-encapsulated semiconductor device suited to a ball-grid-array (BGA) semiconductor device. The present invention also relates to a method for fabricating such a semiconductor device.
DESCRIPTION OF RELATED ART
For reduction of dimensions of semiconductor devices, BGA semiconductor devices have been increasingly used these days.
FIG. 1
shows the structure of a conventional BGA semiconductor device, wherein a semiconductor chip
31
is mounted on a central area of an interposer substrate
32
, and fixed to the interposer substrate
32
with the bottom surface of the semiconductor chip
31
being adhered thereto. The interposer substrate
32
is made of an organic insulating substance such as polyimide, glass epoxy, BT resin etc, on which a metallic interconnect pattern or bonding pad
34
made of Cu, for example, is provided.
The interposer substrate
32
has a plurality of bonding pads
34
in the vicinity of the outer periphery thereof, i.e., outside the area for mounting the semiconductor chip
31
. The inner side
35
of the bonding pad
34
is called stitch area and used for connection with a bonding wire
40
, whereas the outer side
36
of the bonding pad
34
is called land area on which a solder ball
38
is formed. The organic insulator
37
of the interposer substrate
32
has an opening for the land area
36
, on the bottom surface of which the solder ball
38
is formed. The solder ball
38
is used as an external terminal by an end user for mounting the semiconductor device on a printed circuit board.
The mounting of the semiconductor chip
31
onto the interposer substrate
32
is conducted as follows. First, a specified amount of adhesive
33
is dropped onto a specified position of the interposer substrate
32
from a multi-nozzle coater, then a semiconductor chip
31
is mounted thereto, and the adhesive
33
is cured by heating to fix the semiconductor chip
31
onto the interposer substrate
32
. Subsequently, Al chip electrodes
39
and the stitch area
35
of the bonding pads
34
are electrically connected together by a wire bonding technique using bonding wires
40
made of Au or Cu. Thereafter, the top surface of the interposer substrate
32
together with the semiconductor chip
31
is encapsulated by a transfer molding technique using a mold resin
41
containing therein an epoxy resin as a main component thereof, whereby the semiconductor chip
31
is protected against mechanical damages thereof and ingress of moisture.
Subsequently, solder balls
38
constituting external terminals are formed on the bottom surfaces of the land areas
36
of the bonding pads
34
on the interposer substrate
32
. In this step, flux is applied onto the land areas
36
beforehand, then the solder balls
38
are placed onto the land areas
36
, followed by thermal reflow of the solder ball
38
to form the external terminals
38
therefrom. The external terminals
38
are made of solder including tin and lead as the main components thereof, for example.
In the conventional BGA semiconductor device as to described above, the two layer structure of the interposer substrate including the organic insulator and the metallic interconnect pattern prevents a reduction of the thickness of the BGA semiconductor device having the interposer substrate.
Each of Patent Publications JP-A-2-240940, -10-116935 and -11-195733 describes a technique for reducing the thickness of the semiconductor device by polishing the interposer substrate made of resin at the bottom surface thereof.
In the described technique, there is a drawback in which an electrolytic plating technique which allows formation of a metallic interconnect layer having a higher impurity is difficult to use on the resin interposer substrate. Although there is some technique wherein an electrolytic plating technique can be used on the resin substrate by providing an electrode film on the resin substrate, the electrode film must extend to the outer periphery of the resin substrate and thus forms the metallic interconnect pattern at the outer periphery where the metallic interconnect pattern is not needed.
In addition, in the conventional semiconductor device, after the arrangement of the stitch areas for the bonding wires is determined, the locations of the land areas for the bonding pads are determined accordingly at the outside of the stitch areas. This imposes a large restriction on the arrangement of the external terminals, and causes an obstacle against the reduction of the planar dimensions of the electronic appliances or electronic parts mounting thereon the semiconductor device.
In particular, it is requested to reduce the pitch of the external terminals in the semiconductor device along with the recent reduction of the dimensions of the electronic appliances and parts. In this respect, although the pitch reduction for the bonding pads has been achieved to some extent in the metallic interconnect pattern due to the development of the photolithographic technique, the pitch reduction for the external terminals has not been successful due to the large space needed for formation of the solder ball.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to solve the above problem and to reduce the costs and the dimensions of a BGA semiconductor device by improving the structure of the conventional BGA semiconductor device to reduce the overall dimensions thereof and to form a metallic interconnect pattern having an excellent connection capability at a desired position.
The present invention provides, in a first aspect thereof, a semiconductor device including a semiconductor chip having chip electrodes thereon, a metallic interconnect pattern having a top surface connected to the chip electrodes and supporting the semiconductor chip, at least the top surface of the metallic interconnect pattern being formed by an electrolytic plating technique, a insulating film covering a bottom surface of the metallic interconnect pattern and having through-holes therein, a plurality of external terminals formed on the bottom surface of the interconnect pattern in the through-holes, and a mold resin encapsulating the semiconductor chip on the top surface of the metallic interconnect pattern and the insulating film.
In accordance with the semiconductor device of the present invention, by employing a structure wherein only a thin insulator film and an electrolytic-plated interconnect pattern are formed on the bottom surface of the semiconductor chip, the overall thickness of the semiconductor device can be reduced compared to the conventional semiconductor device having the interposer substrate.
In addition, the electrolytic-plated interconnect pattern has an improved reliability, thereby allowing improvements in quality and reduction of dimensions and costs for the electronic appliances and parts mounting thereon the semiconductor device.
The present invention also provides, in a second aspect thereof, a method for forming a semiconductor device including the steps of forming a frame substrate having a metallic plate and a metallic interconnect pattern formed on a top surface of the metallic plate, mounting a semiconductor chip on the interconnect pattern, encapsulating the semiconductor chip on the frame substrate by a mold resin, and removing at least a part of the metallic plate at a bottom surface thereof to expose at least a part of the metallic interconnect pattern.
In accordance with the method of the present invention, the process of removing the metallic plate of the frame substrate to expose the interconnect pattern after encapsulating the semiconductor chip by a mold resin assures an excellent rigidity of the semiconductor device before the encapsulation and reduces the overall thickness of the semiconductor device after the encapsulation.


REFERENCES:
patent: 5592025 (1997-01-01), Clark et al.
patent: 5726489 (1998-03-01), Matsuda et al.
patent: 5729432 (1

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