Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-05-17
2004-07-06
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S699000
Reexamination Certificate
active
06759319
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating semiconductor devices, and more particularly, to the fabrication of solder bumps in the manufacture of an integrated circuit device.
2. Description of the Prior Art
Solder paste bumping is emerging as a strong candidate for a low-capital, low-cost method for producing bumped wafers. In a solder paste bumping process, a solder paste is printed onto the integrated circuit through a stencil. Metal stencils or, in the case of fine geometry, lithographically defined polymeric aperture stencils are used. The printed solder paste is then heated, or reflowed, to cause the solder to form a solder ball. This solder ball, or solder bump, then provides a solderable contact point for directly connecting the integrated circuit to a circuit board.
The cleanliness of the final wafer surface produced using a solder paste print method is an important characteristic. This cleanliness depends on flux chemistry, wafer surface conditions, reflow operations, cleaning methods, and cleaning chemistry. Special cleaning problems arise in the case of polymeric aperture stencils. During high temperature exposure, such as during reflow, excessive cross-linking can occur in the polymeric material. This cross-linking phenomenon makes it difficult to remove all of the polymeric material following the formation of the solder bumps.
Several prior art approaches disclose methods to form solder bumps on an integrated circuit device. U.S. Pat. No. 5,767,010 to Mis et al discloses a method to form solder bumps. A titanium barrier layer is formed on the substrate prior to deposition of the underbump metallurgy (UBM) layer. Neither the UBM nor the titanium barrier layer is patterned until after the solder bumps are deposited and reflowed. U.S. Pat. No. 5,892,179 to Rinne et al teaches a method to form a solder bump with an elongated UBM structure that allows an offset between the solder bump and the contact pad. A titanium barrier layer is disclosed in a co-assigned patent application referenced therein. U.S. Pat. No. 4,273,859 to Mones et al discloses a method to form solder bump pads wherein a barrier layer is deposited between the contact pads and the solder bumps. U.S. Pat. No. 5,672,542 to Schwiebert et al teaches a method to form solder bumps. Solder is applied through a stencil that remains in place during reflew. U.S. Pat. No. 5,024,372 to Altman et al discloses a method to form solder bumps wherein a solder resist is applied and patterned to create wells. Solder paste is then applied and reflowed to form bumps. U.S. Pat. No. 5,194,137 to Moore et al teaches a solder bump method. A terminal pad with a connected linear runner is formed on the substrate. A solder alloy is applied. During reflow, solder is drawn from the runner to the terminal pad to form a raised bump. U.S. Pat. No. 5,400,950 to Myers et al discloses a method to form solder bumps wherein the bump height is carefully controlled while improved thermal cycle and mechanical capability is achieved. Non-input/output, or dummy, bumps are used.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating solder bumps in the manufacture of integrated circuit devices.
A further object of the present invention is to provide a method to fabricate solder bumps that produces wafers free from flux, polymeric residue, and contamination.
A yet further object of the present invention is to prevent contamination through the use of a sacrificial layer underlying the aperture mask.
Another yet further object of the present invention is to provide a solder bumping method that is free of residues and is compatible with electroless plated UBM.
Another yet further object of the present invention is to provide a solder bumping method suitable for any type of polymeric stencil.
Another yet further object of the present invention is to provide a solder bumping method suitable for either lead-base and lead-free solder pastes.
In accordance with the objects of this invention, a new method of fabricating solder bumps in the manufacture of an integrated circuit device has been achieved. Contact pads are provided overlying a semiconductor substrate. A passivation layer is provided overlying the contact pads. The passivation layer has openings that expose a top surface of the contact pads. A sacrificial layer is deposited overlying the passivation layer and the exposed top surface of the contact pads. The sacrificial layer is not wettable to solder. Under bump metallurgy (UBM) caps may be formed either by deposition and patterning of a UBM layer stack or by selective electroless deposition of a material such as nickel. An aperture mask is formed overlying the sacrificial layer. The aperture mask has openings that expose a part of the sacrificial layer overlying the contact pads. A solder layer is deposited into the openings in the aperture mask. The solder layer is reflowed to form solder bumps overlying the contact pads. The aperture mask is stripped away. The sacrificial layer is etched away to complete the formation of the solder bumps in the manufacture of the integrated circuit device. The etching away of the sacrificial layer insures the complete removal of all of the residue of the aperture mask.
REFERENCES:
patent: 4273859 (1981-06-01), Mones et al.
patent: 5024372 (1991-06-01), Altman et al.
patent: 5194137 (1993-03-01), Moore et al.
patent: 5400950 (1995-03-01), Myers et al.
patent: 5672542 (1997-09-01), Schwiebert et al.
patent: 5767010 (1998-06-01), Mis et al.
patent: 5892179 (1999-04-01), Rinne et al.
patent: 6222279 (2001-04-01), Mis et al.
patent: 6232212 (2001-05-01), Degani et al.
patent: 6281106 (2001-08-01), Higdon et al.
patent: 6310403 (2001-10-01), Zhang et al.
patent: 6338985 (2002-01-01), Greenwood
patent: 6340608 (2002-01-01), Chooi et al.
Viswanadam Gautham
Wong Chee Chong
Ackerman Stephen B.
Cuneo Kamand
Institute of Microelectronics
Saile George O.
Sarkar Asok Kumar
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