Reshuffled communications processes in pipelined...

Electrical computers and digital data processing systems: input/ – Intrasystem connection

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S001000, C710S052000, C712S001000, C712S010000, C712S011000, C712S220000, C712S219000, C712S225000, C708S233000, C708S508000, C326S038000, C326S041000, C370S298000, C377S066000, C377S070000, C377S073000, C377S074000, C377S075000, C377S079000, C377S081000, C365S189011, C365S189040, C365S189050, C365S189140, C365S189150, C365S189160, C716S030000

Reexamination Certificate

active

07934031

ABSTRACT:
An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.

REFERENCES:
patent: 3290511 (1966-12-01), Sims, Jr.
patent: 4680701 (1987-07-01), Cochran
patent: 4710650 (1987-12-01), Shoji
patent: 4875224 (1989-10-01), Simpson
patent: 4912348 (1990-03-01), Maki et al.
patent: 5367638 (1994-11-01), Niessen et al.
patent: 5434520 (1995-07-01), Yetter et al.
patent: 5440182 (1995-08-01), Dobbelaere
patent: 5479107 (1995-12-01), Knauer
patent: 5544342 (1996-08-01), Dean
patent: 5572690 (1996-11-01), Molnar
patent: 5666532 (1997-09-01), Saks et al.
patent: 5732233 (1998-03-01), Klim et al.
patent: 5737614 (1998-04-01), Durham et al.
patent: 5752070 (1998-05-01), Martin et al.
patent: 5802331 (1998-09-01), Van Berkel
patent: 5889979 (1999-03-01), Miller, Jr. et al.
patent: 5918042 (1999-06-01), Furber
patent: 5920899 (1999-07-01), Chu
patent: 5949259 (1999-09-01), Garcia
patent: 5973512 (1999-10-01), Baker
patent: 6038656 (2000-03-01), Martin et al.
patent: 6044453 (2000-03-01), Paver
patent: 6049882 (2000-04-01), Paver
patent: 6055620 (2000-04-01), Paver et al.
patent: 6152613 (2000-11-01), Martin et al.
patent: 6301655 (2001-10-01), Manohar et al.
patent: 6381692 (2002-04-01), Martin et al.
patent: 6502180 (2002-12-01), Martin et al.
patent: 6658550 (2003-12-01), Martin et al.
patent: 2002/0156995 (2002-10-01), Martin et al.
patent: WO9207361 (1992-04-01), None
Venkat et al., “Timing Verification of Dynamic Circuits”, May 1, 1995, IEEE 1995 Custom Integrated Circuits Conference.
Wilson, “Fulcrum IC heats asynchronous design debate”, Aug. 20, 2002, http://www.fulcrummicro.com/press/article—eeTimes—08-20-02.shtml.
Martin, “Asynchronous Datapaths and the Design of an Asynchronous Adder”, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 1-24.
Martin, “Self-Timed FIFO: An Exercise in Compiling Programs into VLSI Circuit”, Computer Science Department California Institute of Technology, pp. 1-21.
A. J. Martin, “Synthesis of Asynchronous VLSI Circuits”, Dept. of Computer Science, California Institute of Technology, Pasadena, CA, Aug. 9, 1991, 147 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Reshuffled communications processes in pipelined... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reshuffled communications processes in pipelined..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reshuffled communications processes in pipelined... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2731097

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.