Resetting of multiple processors in an electronic device

Details Resetting of multiple processors in an electronic device Resetting of multiple processors in an electronic device

2011-03-29

2011-03-29

Iqbal, Nadeem (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

07917812

ABSTRACT:
Automatic resetting of a group of multiple processors in an electronic device wherein the processors are arranged in either a cascade chain or master-slave configuration. Upon the receipt of an originating reset signal by any one of the multiple processors the remaining processors are reset upon receipt of a forced reset signal generated by one of the processors in the group. The system states prior to the originating reset of each processor is refreshed to ensure compatible synchronization of system states and thus proper communication among the processors.

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