Resetting arrangement for a semiconductor integrated circuit dev

Details Resetting arrangement for a semiconductor integrated circuit dev Resetting arrangement for a semiconductor integrated circuit dev

1986-05-07

1988-07-19

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365203, G11C 700

Patent

active

047589906

ABSTRACT:
A semiconductor integrated circuit device having a semiconductor memory wherein part of the operation of a half precharge circuit is stopped by a reset signal, complementary data lines are set to high and low levels and a plurality of word lines are simultaneously brought into a selection state in order to effect a reset operation at a high speed.

REFERENCES:
patent: 4099265 (1978-07-01), Abe
patent: 4379344 (1983-04-01), Ozawa et al.

Affiliated with

Also associated with

Rating

Resetting arrangement for a semiconductor integrated circuit dev does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Resetting arrangement for a semiconductor integrated circuit dev, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Resetting arrangement for a semiconductor integrated circuit dev will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-601525