Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1998-08-18
2001-08-14
Hjerpe, Richard (Department: 2783)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C501S065000, C501S065000
Reexamination Certificate
active
06275951
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reset signal control circuit of a one-chip microcomputer, and more particularly, to a reset signal control circuit for reducing the size of the chip and reducing the test time of the chip.
2. Discussion of the Related Art
A microcomputer is a kind of computer system usually used in data storage and retention, numerical computation, and control measurement of mechanical devices, and comprises memories, a central processing unit, peripheral devices and input/output(I/O) ports. Such a microcomputer can be implemented on a single chip as the semiconductor technologies has been developed, and particularly is referred to as a one-chip microcomputer.
FIG. 1
shows a structure of a one-chip microcomputer according to the prior art. A memory
1
, a central processing unit(CPU)
2
, a peripheral device
3
and an input/output port
4
are organically connected by address buses and data buses, enabling mutual exchanges of addresses and data.
FIG. 1
also shows a clock oscillation circuit
5
for generating clock signals and a timer
10
which is necessary to control interior reset signals. Input signals of the clock oscillation circuit
5
includes an input oscillation signal XIN and an oscillation enable signal OSC, and an output signal includes an output oscillation signal XOUT. The input oscillation signal XIN is output from an oscillation means such as a crystal oscillator populated on a printed circuit board outside of the chip and provided to the inside of the chip, and the output oscillation signal XOUT is an oscillation signal which is provided to the oscillation means outside from inside of the chip. The oscillation enable signal OSC is a signal for driving the clock oscillation circuit
5
, and its activation is determined by a power saving mode signal STP, an exterior reset signal RST_EX and an exterior interrupt signal /INTRP.
The power saving mode signal STP causes a power saving mode in which almost all of the hardware of the system is not operated when operation of the clock oscillation circuit
5
is stopped. Thus, in the power saving mode, the clock signal is not generated.
A construction of a logical gate for generating control signals of the clock oscillation circuit
5
in
FIG. 1
is as follows. First, the exterior reset signal RST_EX is provided to an OR gate
7
and at the same time, the exterior interrupt signal /INTRP which is an active low signal is inverted and then provided to the OR gate
7
. An output signal of the OR gate
7
is provided to another OR gate
8
together with the power saving mode signal STP. An output signal of the OR gate
8
is a control signal for controlling oscillating operation of the clock oscillation circuit
5
.
In order to activate the oscillation enable signal OSC of the clock oscillation circuit
5
to a high level (to produce the power saving mode) both the power saving mode signal STP from the CPU
2
and the output of the OR gate
7
should be at a low level. As such, the exterior interrupt signal /INTRP should be at a high level and exterior reset signal RST_EX should be at a low level. That is, (the /INTRP signal goes to a low level, if an interrupt from the outside occurs in the power saving mode (the /INTRP signal goes to a low level); or if the system is reset (the RST_EX goes to a high level), the clock oscillation circuit
5
is enabled to operate.
The output oscillation signal XOUT from the clock oscillation circuit
5
is provided to the CLK input of the timer
10
for generating the interior reset signal RST_IN. And the exterior interrupt signal /INTRP is inverted and then provided to the START input of the timer
10
to be used as an operation start signal. That is, if the exterior interrupt signal /INTRP is activated as a low level, the timer
10
starts an operation, causing the interior reset signal RST_IN of high level to be output from the OR gate
6
and after a predetermined time, inactivating the interior reset signal RST_IN to be a low level. Another input of the OR gate
6
is an exterior reset signal RST_EX. Accordingly, if an interrupt the outside from the outside is occurred or the system is reset, the interior reset signal RST_IN is activated. The interior reset signal RST_IN is provided to the CPU
2
, the peripheral device
3
and the I/O port
5
, initializing the system.
An activating time of an activating signal (for outputting the interior reset signal RST_IN of the level from the OR gate
6
) from the timer
10
is maintained until the oscillation operation of the clock oscillation circuit
5
is stabilized when the exterior interrupt signal /INTRP is activated in the power saving mode state. The reason is that a predetermined oscillation stabilization time is required until a stabilized level of the clock signal is output from the clock oscillation circuit
10
. If the system starts its operation in the state that the clock oscillation circuit
5
is not yet stabilized, a normal operation of the system can not be expected because of a unstable level of the clock signal.
Accordingly, in the power saving mode, the timer
10
produces an activated interior reset signal RST_IN from the time when the exterior interrupt signal /INTRP is activated to the time after which the clock oscillator
5
has been stabilized even though the exterior interrupt signal /INTRP is activated and the operation of the clock oscillation circuit
5
is started. The clock oscillation circuit
5
is stabilized and produces a normal level output oscillation signal XOUT during the activating time of the interior reset signal RST_IN.
FIG. 2
shows a timing diagram representing the reset signal control operation of the prior art one-chip microcomputer. In
FIG. 4
, I represents a power saving mode signal (STP), II represents an output oscillation signal (XOUT), III represents an exterior interrupt signal (/INTRP), and IV represents an output signal (RST_IN) (i.e., interior reset signal) of the timer.
When the power saving mode signal I is in the low level, an oscillation operation is occurred in the clock oscillation circuit and thus the output oscillation signal II is a normal oscillation signal. However, when the power saving mode signal I is in the high level, the oscillation operation is not occurred in the clock oscillation circuit and thus the output oscillation signal II is in the low level. In the state that the power saving mode signal I is in the low level, when the exterior interrupt signal III is activated to the low level, the output signal IV of the timer goes to the high level. In this state, the output signal IV of the timer is inactivated again to the low level after a predetermined delay time set in the timer.
The time required for a clock stabilization is determined in consideration of the restriction of the frequency of a crystal oscillator, supply voltage and routing. When populating the one-chip microcomputer on a printed circuit board, the distance between the CPU of the chip and the oscillation means in the outside of the chip should be maintained as short as possible. However, if considering the position of the peripheral devices in an actual routing, the distance between the oscillation means and the CPU is far away, and thus the routing may be lengthened and also may be very complicated. Since such a long routing or such a complicated routing between the exterior oscillation means and the CPU may cause a pseudo oscillation hence, a normal operation of the oscillation means can not be expected.
Since an activating time of the interior reset signal RST_IN is continued in the timer
10
until the clock oscillation circuit
5
is sufficiently stabilized, a stabilized activating time of the reset signal is ensured by considering a constitution of the exterior circuit which was not optimized as described above and providing some marginal time in addition to the absolute time required for stabilizing the clock oscillation circuit
5
.
However, a plurality of transistors are actually required in order to implement such
Hjerpe Richard
Hyundai Electronics Industries Co,. Ltd.
Monestime Mackly
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