Reset logic circuit and method

Details Reset logic circuit and method Reset logic circuit and method

1993-04-19

1995-07-04

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

327198, 327208, H03K 1920, H03K 326

Patent

active

054303990

ABSTRACT:
A high speed inverter circuit is disclosed. The inverter has a quiescent state, a set state for receiving an input pulse and generating a set pulse in response thereto, a reset stage in which a delayed version of the same input pulse is used to reset the inverter, and a recovery state for preparing the inverter for the arrival of a new input pulse. The inverter has an extremely fast switching speed because virtually all of the available energy of the input signal is used to set the inverter. The inverter may be used in an inverter chain for rapidly propagating electrical signals.

REFERENCES:
patent: 4513329 (1985-04-01), Gomez et al.
patent: 4728820 (1988-03-01), Lee
patent: 4806786 (1989-02-01), Valentine
patent: 4985643 (1991-01-01), Proebsting
Technische Rundschau, vol. 68, No. 51, Dec. 1976, Bern Ch., pp. 9-11, P. Blomeyer, "Kleines LSL-Praktikum", (p. 9, Para 2.2.2, FIG. 19).

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