Reset design for redundant raid controllers

Details Reset design for redundant raid controllers Reset design for redundant raid controllers

1998-08-07

2000-07-04

Sheikh, Ayaz R.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

710 1, 711114, G06F 300

Patent

active

060853328

ABSTRACT:
A reset circuit implemented in a RAID controller configured for dual active operation. The reset circuit generates a reset pulse with a relatively invariant pulse width that is coupled to the controller's main CPU and I/O processors. The reset pulse can be generated in response to activation of an external common reset signal. The external common reset signal is activated by an external system (e.g., another controller configured for dual active operation) whenever the controller needs to be reset. This can be when the controller fails to maintain a communication signal transmitted to the external system or when the external system has inconsistent configuration information, requiring the entire system (i.e., both the controller and the external system) to be re-initialized. The reset pulse can also be generated in response to internal reset instructions issued by the controller's main CPU. The reset instructions can be issued whenever the first controller determines that its own configuration information is inconsistent. As a result of the reset instruction being issued the external common reset signal is activated as an output to reset the external system (i.e., the external common reset signal is bidirectional). The self-reset operation can be over-ridden by a reset disable instruction.

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