Reset control system and method

Details Reset control system and method Reset control system and method

2005-04-05

2005-04-05

Beausoliel, Robert (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S011000, C714S012000, C703S023000

Reexamination Certificate

active

06877112

ABSTRACT:
An OR circuit (34, 35) OR-operates an emulator reset signal (106, 107) based on a reset instruction from an emulator (30) and an external reset signal (115, 116) supplied from an external reset generation circuit. The OR operation result is distributed and supplied to a processor (10) and a companion chip (20) as a system reset signal (109, 110), thereby initializing both chips of the processor (10) and the companion chip (20) in accordance with the reset the emulator (30).

REFERENCES:
patent: 5630102 (1997-05-01), Johnson et al.
patent: 6175914 (2001-01-01), Mann
patent: 6226756 (2001-05-01), Mueller
patent: 6367032 (2002-04-01), Kasahara
patent: 6415393 (2002-07-01), Satoh
patent: 6564339 (2003-05-01), Swoboda et al.
patent: 64-55652 (1989-03-01), None

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