Reset circuit for resetting two clock domains

Details Reset circuit for resetting two clock domains Reset circuit for resetting two clock domains

2007-06-12

2007-06-12

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

Reexamination Certificate

active

10885922

ABSTRACT:
A reset circuit for resetting two clock domains resets the two clock domains synchronously with a first clock signal in response to assertion of a system reset. It then de-asserts the resetting of a first of the clock domains in synchronization with the first clock signal, and de-asserts the resetting of a second of the clock domains in synchronization with a second clock signal so that the second clock domain is not operative until after the second clock signal is running.

REFERENCES:
patent: 6055285 (2000-04-01), Alston
patent: 6370644 (2002-04-01), LaBerge
patent: 6586969 (2003-07-01), Koe
patent: 6748039 (2004-06-01), Bates

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