Reset circuit and FeRAM using the same

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit

Reexamination Certificate

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C365S189090

Reexamination Certificate

active

06870779

ABSTRACT:
A reset signal generating circuit and a nonvolatile ferroelectric memory device using the same are disclosed. The reset signal generating circuit generates a reset signal by using a self-bias circuit regardless of a slope time of a power voltage only when the power voltage rises beyond a predetermined voltage. As a result, the reset signal generating circuit may generate a stable reset signal having excellent operation characteristics at short intervals even when the supply of the power source is repeatedly intercepted. Additionally, the reset signal generation circuit may stabilize generation of control signals for controlling a nonvolatile FeRAM, thereby improving the operation characteristics of the memory device.

REFERENCES:
patent: 5305269 (1994-04-01), Vinal
patent: 5376835 (1994-12-01), Van Buskirk et al.
patent: 5508649 (1996-04-01), Shay
patent: 5519347 (1996-05-01), Kim
patent: 5610542 (1997-03-01), Kang et al.
patent: 5617062 (1997-04-01), O'Shaughnessy et al.

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