Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-28
2003-06-03
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S293000, C257S294000, C257S296000, C365S145000, C365S149000, C365S161000, C327S142000, C327S143000, C327S147000, C307S402000, C307S402000, C324S10300R, C324S072000, C324S457000
Reexamination Certificate
active
06573543
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority to Japanese Patent Application Number 2000-297663 filed Sep. 28, 2000, the content of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reset device (or apparatus) for detecting, for example, a rise of a supply voltage so as to start outputting a reset signal and then releasing the reset signal, and a semiconductor IC apparatus (or device) and a semiconductor memory apparatus (or device) including the reset device.
2. Description of the Related Art
Conventional techniques for resetting for initialization of a system include, for example, (i) so-called hardware reset by which the system is allowed to be initialized from a terminal dedicated to resetting, asynchronously with the operation of the system, (ii) power-on reset by which a reset signal for initializing a system is automatically generated when the power is turned on, and (iii) software reset by which the system is initialized by generating a reset signal by interpreting a command which is input from an external device. The power-on reset used in a conventional reset device will be described.
The reset device includes a supply voltage detection circuit for detecting a supply voltage by some method in order to determine whether the power is turned on or not, and a reset signal output circuit for starting to output a reset signal and then releasing the reset signal based on the detection of the supply voltage.
FIG. 4
shows a simple example of a circuit configuration of such a conventional reset device. Referring to
FIG. 4
, a reset device
100
includes a supply voltage detection circuit
101
including a capacitor C (dielectric capacitor) and a resistor R connected in series, and a reset signal output circuit
104
including a first-stage inverter
102
and a second-stage inverter
103
connected in series. The inverters
102
and
103
each include a p-channel MOS transistor (hereinafter, referred to as the “p-channel Tr) and an n-channel MOS transistor (hereinafter, referred to as the “n-channel Tr).
Due to the above-described structure, when the supply voltage rises, the capacitor C of the supply voltage detection circuit
101
is charged through the resistor R at a prescribed time constant RC. The voltage which is generated at the resistor R by the charging current is given to the first-stage inverter
102
, including the p-channel Tr and the n-channel Tr, through a node N
105
. At this point, the capacitor C is not charged rapidly. The node N
105
is in a logical “low” state, and the reset signal which is output from the reset signal output circuit
104
is also in an active logical “low” state.
Next, when the potential of the node N
105
increases as the capacitor C is more and more charged and exceeds a gate threshold voltage which is mainly determined by the threshold voltages and the driving capabilities of the p-channel Tr and the n-channel Tr of the first-stage inverter
102
, the output of the first-stage inverter
102
inverts to a logical “low” state. The logical “low” output is sent to the second-stage inverter
103
, and inverted into a logical “high” state. Thus, the reset signal which is output from the reset signal output circuit
104
is released. A value of the time constant RC of the capacitor C and the resistor R (C×R) is appropriately selected so that the supply voltage is at a sufficiently high level for a sufficiently long reset time which is required for the system. The reset time is a time period from when the output of the reset signal is started until the reset signal is released.
However, when the rise of the supply voltage when the power is turned on is sufficiently slow such that the capacitor C is fully charged only at the end of a duration corresponding to the time constant RC, there is an undesirable possibility that the potential of the node N
105
does not reach the gate threshold voltage of the inverter
102
, and as a result, the reset signal from the reset signal output circuit
104
may not be released.
In order to avoid such an inconvenience, a reset signal device
200
shown in
FIG. 5
including a supply voltage detection circuit dedicated to the case when the supply voltage slowly rises and another supply voltage detection circuit dedicated to the case when the supply voltage rapidly rises is used. Referring to
FIG. 5
, the reset device
200
includes a supply voltage detection circuit
201
operating when the supply voltage slowly rises, a supply voltage detection circuit
202
operating when the supply voltage rapidly rises, and a reset signal output circuit
203
for starting to output a reset signal and releasing the reset signal in accordance with signals input from the supply voltage detection circuit
201
and
202
.
The supply voltage detection circuit
201
has the following structure. Resistors R
1
and R
2
are connected in series between a power supply and the ground. A node N
1
, which is a dividing point (i.e., a connection point) between the resistors R
1
and R
2
, is connected to one of two ends of a capacitor C
1
(dielectric capacitor) and to a gate of an n-channel Tr M
1
. The other end of the capacitor C
1
is connected to the power supply. A source of the n-channel Tr M
1
is grounded, and a drain of the n-channel Tr M
1
is connected to the power supply via a pull-up resistor R
3
. A node N
2
, which is a connection point between the n-channel Tr M
1
and the pull-up resistor R
3
, is connected to an input end of an inverter
210
including a p-channel Tr M
2
and an n-channel Tr M
3
.
The supply voltage detection circuit
202
has the following structure. A p-channel Tr M
4
, a resistor R
4
, and an n-channel Tr M
5
and another n-channel Tr M
6
each having a gate connected to a power supply are connected in series in this order. A node N
3
, which is a connection point between the n-channel Tr M
5
and the resistor R
4
, is connected to a capacitor C
2
(dielectric capacitor) and to an input end of an inverter
220
including a p-channel Tr M
7
and an n-channel Tr MB. To a gate of the p-channel Tr M
4
, a reset signal is input as a result of being fedback.
The reset signal output circuit
203
includes a negative OR circuit, which includes a NAND circuit NAND
1
for receiving an output from each of the supply voltage detection circuits
201
and
202
, and an inverter
230
for receiving an output from the NAND circuit NAND
1
and starting to output a reset signal or releasing the reset signal. The inverter
230
includes a p-channel Tr M
9
and an n-channel Tr M
10
.
The n-channel Trs M
8
and M
10
each have a low threshold voltage, and thus are specifically indicated as in FIG.
5
.
Hereinafter, an operation of the reset device
200
when the supply voltage slowly rises will be described.
Immediately after the power is turned on, the potential of the node N
2
is in a logical “high” state as a result of being pulled up via the resistor R
3
. Therefore, the output from the inverter
210
(i.e., the output from the supply voltage detection circuit
201
) is in a logical “low” state. Thus, the output from the NAND circuit NAND
1
is in a logical “high” state regardless of whether the input from the supply voltage detection circuit
202
is in a logical “high” state or a logical “low” state. Therefore, the reset signal, which is output from the inverter
230
(i.e., the output from the reset signal output circuit
203
), is in an active logical “low” state (i.e., the state of outputting a reset signal).
In the case where the supply voltage slowly rises, even when a sufficient amount of current does not flow into the capacitor C
1
, a potential which is lower than the supply voltage divided into the resistors R
1
and R
2
connected in series is input to the gate of the n-channel Tr M
1
via the node N
1
. When the potential of the node N
1
exceeds the threshold voltage of the n-channel Tr M
1
, the n-channel Tr M
1
is activated. Therefore, the node N
2
is transferred fr
Erdem Fazli
Flynn Nathan J.
Morrison & Foerster / LLP
Sharp Kabushika Kaisha
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