Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-11-02
2001-08-14
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S120000, C711S122000, C711S144000, C711S145000, C711S121000
Reexamination Certificate
active
06275907
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to a method and system for data processing and, in particular, to data processing within a non-uniform memory access (NUMA) data processing system. Still more particularly, the present invention relates to a NUMA data processing system and method of reservation management in a NUMA data processing system.
2. Description of the Related Art
In shared memory multiprocessor (MP) data processing systems, each of the multiple processors in the system may access and modify data stored in the shared memory. In order to synchronize access to a particular granule (e.g., cache line) of memory between multiple processors, load-reserve and store-conditional instructions are often employed. For example, load-reserve and store-conditional instructions have been implemented in the PowerPC™ instruction set architecture with opcodes associated with the LARX and STCX mnemonics, respectively.
In bus-based shared memory MP data processing systems that support load-reserve and store-conditional instructions, each processor within the system is equipped with a reservation register. When a processor executes a load-reserve to a memory granule, the processor loads some or all of the contents of the memory granule into one of the processor's internal registers and the address of the memory granule into the processor's reservation register. The requesting processor is then said to have a reservation with respect to the memory granule. The processor may then perform an atomic update to the reserved memory granule utilizing a store-conditional instruction.
When a processor executes a store-conditional to a memory granule for which the processor holds a reservation, the processor stores the contents of a designated register to the memory granule and then clears the reservation. If the processor does not have a reservation for the memory granule, the store-conditional instruction fails and the memory update is not performed. In general, the processor's reservation is cleared if a remote processor requests exclusive access to the memory granule for purposes of modifying it (the request is made visible to all processors on the shared bus) or the reserving processor executes a store-conditional instruction. If only one reservation is permitted per processor, a processor's current reservation will also be cleared if the processor executes a load-reserve to another memory granule.
Recently, there has been increased interest in a shared memory MP architecture known as non-uniform memory access (NUMA). A typical NUMA system includes a number of processing nodes, each containing one or more processors, a local system memory, and other devices coupled to a local interconnect. The processing nodes are interconnected by a relatively high latency node interconnect. Because store operations performed by a processor in one processing node are not necessarily made visible to all other processors in a NUMA system, the reservation management techniques utilized in shared-bus MP data processing systems cannot be directly applied to NUMA computer systems. Consequently, in NUMA computer systems, a global reservation directory has been employed within each processing node to maintain reservations of all processors within the system for memory granules in the local system memory. This global implementation of reservation management is somewhat problematical because as additional processing nodes are added to the NUMA computer system, the number of processors can exceed the size of the global reservation directory at each processing node. In addition, it is desirable to permit the processing nodes to support diverse numbers of processors and different processor configurations; however, it may be difficult to number or tag diverse processors in a consistent manner across all processing nodes so that the processors'reservations can be appropriately tracked in the global reservation directories.
As should thus be apparent, it would be useful and desirable to provide a NUMA computer system having an improved method and system for reservation management.
SUMMARY OF THE INVENTION
In accordance with the present invention, a non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules (e.g., cache lines) and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node.
In the course of executing instructions, the processor within the remote processing node may execute a load-reserve instruction, which causes a specified cache line to be loaded into the processor's cache hierarchy and a reservation for the cache line to be set within the processor. If the processor subsequently loads a number of cache lines that map to the same congruence class of the cache hierarchy that contains the reserved cache line, the reserved cache line may be castout through conventional cache line replacement. The reservation is not affected by the replacement of the reserved cache line. According to the present invention, if the processor within the remote processing node has a reservation for a cache line that is not resident within its associated cache hierarchy, the coherence directory at the home processing node associates the cache line with a coherence state indicating that the reserved cache line may possibly be held non-exclusively at the remote processing node. In this manner, the cache coherence mechanism can be utilized to manage processor reservations even in cases in which a reserving processor's cache hierarchy does not hold a copy of the reserved cache line.
The coherence state of the reserved cache line is set to the non-exclusive (e.g., shared) state in response to a writeback transaction transmitted from the remote processing node to the home processing node. In an embodiment of the present invention in which all cache line reservations are made visible (i.e., a processor cannot obtain a “silent” reservation for a cache line resident in its cache hierarchy), the replacement of a reserved cache line causes the reserving processor to issue a writeback-kill transaction indicating that the coherence indicator at the home processing node should be updated to an invalid state. In response to receipt of such a writeback-kill transaction while the reservation is valid, a node controller at the remote processing node converts the writeback transaction to a writeback-clean transaction, thereby indicating that the coherence indicator should be updated to the non-exclusive (e.g., shared) state.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5742785 (1998-04-01), Stone et al.
patent: 5784697 (1998-07-01), Funk et al.
patent: 6073211 (2000-06-01), Cheng et al.
Baumgartner Yoanna
Carpenter Gary Dale
Dean Mark Edward
Elman Anna
Fields, Jr. James Stephen
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Nguyen Hiep T.
Salys Casimer K.
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