Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
2006-11-07
2006-11-07
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Access arbitrating
C710S309000
Reexamination Certificate
active
07133950
ABSTRACT:
A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes an arbiter configured to arbitrate multiple requests received from the plurality of processing cores with available outputs. The arbiter includes a barrel shifter configured to rotate the multiple requests for dynamic prioritization, and priority encoders associated with each of the available outputs. Each of the priority encoders have logic gates configured to disable priority encoder outputs. A method for arbitrating requests within a multi-core multi-thread processor is included.
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Yuval Tamir et al: “Symmetric Crossbar Arbiters for VLSI Communication Switches” IEEE Transactions on Parallel and Distributed Systems, IEEE Service Center, Los Alamitos, CA, US, vol. 4, No. 1, Jan. 1993, pp. 13-27, XP000381 ISSN:1045-9219.
Martine & Penilla & Gencarella LLP
Phan Raymond N
Rinehart Mark H.
Sun Microsystems Inc.
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