Request arbitration device and memory controller

Details Request arbitration device and memory controller Request arbitration device and memory controller

2011-04-12

2011-04-12

Song, Jasmine (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S133000, C711S136000, C711S151000, C711S158000, C711S159000

Reexamination Certificate

active

07925849

ABSTRACT:
A bus arbiter receives requests of initiators, and internally includes a page hit/miss determining unit with permissible determining function, a bank open/close determining unit with permissible determining function, and an LRU unit with permissible determining function. Regarding the priority of the request arbitration on the requests, the bank priority on the SDRAM is determined in the order of page hit, bank open, and LRU. Furthermore, each determining unit internally includes a permissible time determining unit, and processes, at top priority, the request of the initiator which the corresponding permissible time is below the count threshold value in the priority processing of the determining unit.

REFERENCES:
patent: 2006/0004956 (2006-01-01), Madajczak
patent: 2006-099199 (2006-04-01), None

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