Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2001-09-21
2002-11-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S185010, C365S203000
Reexamination Certificate
active
06477103
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of reprogrammable fuses and more particularly to a reprogrammable fuse using a pair of non-volatile memory cells having floating gates for storing charges thereon in which the cells are differentially sensed.
BACKGROUND OF THE INVENTION
Reprogrammable fuses are well-known in the art. See, for example, U.S. Pat. No. 6,222,765 which discloses a non-volatile flip flop circuit in which a pair of non-volatile memory cells differentially store charges thereon. In addition, the two cells are connected to a volatile flip flop for faster access.
A non-volatile memory cell of the split gate floating gate type is also well-known in the art. See, for example, U.S. Pat. Nos. 5,029,130 and 5,572,054, whose disclosures are incorporated herein in their entirety by reference. As disclosed in these patents, the non-volatile memory cell comprises a first terminal and a second terminal with a channel therebetween. A floating gate is formed over a first portion of the channel and is insulated therefrom and is over a portion of the first terminal. The non-volatile memory cell also comprises a control gate which overlaps a second portion of the channel. The action of erase, programming, and read are disclosed in the aforementioned patents.
SUMMARY OF THE INVENTION
A reprogrammable fuse comprises a first and a second non-volatile memory cell. Each non-volatile memory cell is of the type having a first terminal and a second terminal in a substrate with a channel therebetween. Each of the first and second non-volatile memory cells has a floating gate for storing charges with the floating gate overlying a portion of the channel and is capacitvely coupled to the first terminal. Each of the first and second non-volatile memory cells further has a control gate overlying a second portion of the channel and serves to remove charges stored on the floating gate. The fuse has a first bitline connected to the second terminal of the first non-volatile memory cell and a second bitline connected to the second terminal of the second non-volatile memory cell. A word line is commonly connected to the control gates of the first and second non-volatile memory cells. A source line is commonly connected to the first terminals of the first and second non-volatile memory cells. A precharging and equalization circuit is commonly connected to the second terminals of the first and second non-volatile memory cells. An output terminal is connected to one of the first or second bitlines for supplying an output signal indicative of the state of the fuse. The fuse is erased by supplying erase voltages to the word line and the source line. The fuse is programmed by supplying programming voltages to the source line, word line, and the first bitline and the second bitline wherein the fuse is programmed to one state or another state. When the fuse is programmed to one state, the floating gate of the first non-volatile memory cell stores more charges than the floating gate of the second non-volatile memory cell. When the fuse is programmed to another state, the floating gate of the first non-volatile memory cell stores less charges than the floating gate of the second non-volatile memory cell. The programmed state of the fuse is read by supplying a precharging voltage to the first and second bitlines with the first and second bitlines being differentially sensed.
REFERENCES:
patent: 5729495 (1998-03-01), Madurawe
patent: 5933039 (1999-08-01), Hui et al.
Bui Thuc
Nguyen Hung Q.
Nguyen Sang Thanh
Nguyen Tam M.
Gray Cary Ware & Freidenrich LLP
Le Thong
Nelms David
Silicon Storage Technology, Inc.
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