Reprogrammable addressing process for embedded DRAM

Details Reprogrammable addressing process for embedded DRAM Reprogrammable addressing process for embedded DRAM

1997-12-23

1999-04-20

Mai, Son

Static information storage and retrieval

Read/write circuit

Testing

36523006, 371 212, 371 216, G11C 700

Patent

active

058963316

ABSTRACT:
A functional test on a memory array, formed by a plurality of embedded memory segments each with a reprogrammable address, is conducted by programming the same address into each segment and conducting a portion of the functional test while simultaneously addressing all of the segments using the same reprogrammed address. A test pattern of signals is written into the segments by using the same reprogrammed address, and then unique addresses are reprogrammed after writing the test pattern signals. The signals which were created by writing the test pattern are read by using the unique addresses. The functional test is simplified by using the same address to write the test pattern, rather than generating unique addresses to write the test pattern to all of the memory segments.

REFERENCES:
patent: 4866676 (1989-09-01), Crisp et al.
patent: 5208778 (1993-05-01), Kumanoya
patent: 5231319 (1993-07-01), Crafts et al.
patent: 5270977 (1993-12-01), Iwamoto
patent: 5323348 (1994-06-01), Mori et al.
patent: 5325334 (1994-06-01), Roh et al.
patent: 5373472 (1994-12-01), Ohsawa
patent: 5375095 (1994-12-01), Yamada et al.
patent: 5386386 (1995-01-01), Ogihara
patent: 5388104 (1995-02-01), Shirotori et al.
patent: 5440517 (1995-08-01), Morgan et al.
patent: 5471482 (1995-11-01), Byers et al.
patent: 5502675 (1996-03-01), Kohno et al.
patent: 5517450 (1996-05-01), Ohsawa et al.
patent: 5577004 (1996-11-01), Leshem
patent: 5623640 (1997-04-01), Nakabo
patent: 5650975 (1997-07-01), Hamade et al.
patent: 5668755 (1997-09-01), Hidaka
patent: 5689466 (1997-11-01), Qureshi
patent: 5694355 (1997-12-01), Skjaveland et al.
patent: 5825682 (1998-10-01), Fukui

Affiliated with

Also associated with

Rating

Reprogrammable addressing process for embedded DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reprogrammable addressing process for embedded DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reprogrammable addressing process for embedded DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2252537