Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-16
2007-10-16
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
11060017
ABSTRACT:
Various embodiments of the invention determine whether paths of a first graph satisfy a constraint based on a plurality of sub-graphs of the first graph. Each graph is a directed acyclic graph of nodes and arcs. The first graph and a second graph are generated in a memory arrangement, with the first graph and the second graph having a shared sub-graph, and each path of the paths of the first graph is constrained by the constraint unless the path is a path of the second graph. The plurality of sub-graphs of the first graph are generated in the memory arrangement with each of the plurality of sub-graphs not including any path of the second graph and each of the paths of the first graph that is not a path of the second graph being included in at least one of the plurality of sub-graphs.
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Bixler Matthew
Manaker, Jr. Walter A.
Bowers Brandon W.
Cartier Lois D.
Chiang Jack
Maunu LeRoy D.
Xilinx , Inc.
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