Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-27
2009-11-03
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07614028
ABSTRACT:
Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.
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Office Action dated Jul. 31, 2009 for U.S. Appl. No. 11/741,685.
Notice of Allowance dated Aug. 11, 2009 for U.S. Appl. No. 11/741,694.
Brashears Richard
Nequist Eric
Cadence Design Systems Inc.
Kik Phallaka
Vista IP Law Group LLP
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