Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-25
2008-03-25
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07350172
ABSTRACT:
A method and system are described for generating a performance prediction report to assist finalizing a partitioning scheme of a block diagram model. Providing a user-defined partitioning scheme and information describing a target hardware platform used in that partitioning scheme, the present invention can generate a performance prediction report by analyzing the computational characteristics of the block diagram model.
REFERENCES:
patent: 6647508 (2003-11-01), Zalewski et al.
patent: 6862696 (2005-03-01), Voas et al.
patent: 7007183 (2006-02-01), Rawson, III
patent: 7051309 (2006-05-01), Crosetto
patent: 2004/0111710 (2004-06-01), Chrakadhar et al.
Galijasevic Zijad
Koh David
Orofino, II Donald Paul
Chiang Jack
Lahive & Cockfield LLP
Tat Binh
The MathWorks, Inc.
LandOfFree
Reporting of aspects and partitioning of automatically... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reporting of aspects and partitioning of automatically..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reporting of aspects and partitioning of automatically... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2805360