Replacing layers of an intergate dielectric layer with...

Details Replacing layers of an intergate dielectric layer with... Replacing layers of an intergate dielectric layer with...

2002-05-15

2004-02-17

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000, C257S310000, C257S315000, C257S316000

Reexamination Certificate

active

06693321

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to intergate dielectric layers. In particular, the present invention relates to replacing the layers of an intergate dielectric layer with high-K material for improved scalability.
BACKGROUND
A conventional floating gate FLASH memory device includes a FLASH memory cell characterized by a vertical stack on a semiconductor substrate. The semiconductor substrate is doped with either n-type or p-type impurities to form an active region in the semiconductor substrate. The vertical stack includes a gate dielectric, a floating gate, an intergate dielectric layer and a control gate. The gate dielectric of silicon dioxide (SiO
2
gate dielectric), for example, is formed on the semiconductor substrate. The floating gate (sometimes referred as the “charge storing layer”) of polysilicon, for example, is formed on the gate dielectric. The intergate dielectric layer (e.g., layers of SiO
2
, silicon nitride (“nitride”) and SiO
2
) is formed on the floating gate. The control gate of polysilicon, for example, is formed on the intergate dielectric layer. The floating gate formed on the SiO
2
gate dielectric defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. The source a and drain are formed by dopant impurities introduced into the semiconductor substrate.
Generally speaking, a FLASH memory cell is programmed by inducing hot electron injection from a portion of the semiconductor substrate, such as the channel section near the drain, to the floating gate. Electron injection introduces negative charge into the floating gate. The injection mechanism can be induced by grounding the source and a bulk portion of the semiconductor substrate and applying a relatively high positive voltage to the control gate to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain in order to generate “hot” (high energy) electrons. After sufficient negative charge accumulates in the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel during a subsequent “read” mode. The magnitude of the read current is used to determine whether or not a FLASH memory cell is programmed.
The act of discharging the floating gate of a FLASH memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source of the transistor (source erase or negative gate erase), or between the floating gate and the semiconductor substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source and a 0 V to the control gate and the semiconductor substrate while floating the drain of the respective FLASH memory cell.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, e.g., FLASH memory cells, having feature sizes as small as possible. Many present processes employ features, such as floating gates and interconnects, which have less than a 0.18 &mgr;m critical dimension. As feature sizes continue to decrease, the size of the resulting semiconductor device, as well as the interconnect between semiconductor devices, also decreases. Fabrication of smaller semiconductor devices allows more semiconductor devices to be placed on a single monolithic semiconductor substrate, thereby allowing relatively large circuit systems to is be incorporated on a single, relatively small die area.
As semiconductor device feature sizes decrease, the thicknesses of the SiO
2
layers in the intergate dielectric layer decrease as well. This decrease in SiO
2
layer thickness is driven in part by the demands of overall device scaling. As floating gate widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early semiconductor device scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. A maximum value of semiconductor device subthreshold current can be maintained while feature sizes shrink. Any or all of several quantities may be decreased by appropriate amounts including SiO
2
layer thickness, operating voltage, depletion width, and junction depth, for example.
As a result of the continuing decrease in feature size, SiO
2
layer thickness has been reduced so much that SiO
2
layers of the intergate dielectric layer are approaching thicknesses on the order of ten angstroms (Å). Unfortunately, electrons stored on the floating gate can pass through such thin intergate dielectric layers by quantum mechanical tunneling effect. This charge loss from the floating gate will undesirably alter the memory state stored in the FLASH memory device. This charge leakage due to quantum mechanical tunneling effect increases exponentially with the decrease of the intergate dielectric layer thickness. Therefore, the thickness of the intergate dielectric layer significantly affects the reliability of the floating gate FLASH memory device and is one of the main limiting factor of the scalability of the floating gate memory device.
Another disadvantage of thin SiO2 layers is that a breakdown of the SiO
2
layers may also occur at even lower values of gate voltage, as a result of defects in the SiO
2
layers. Such defects are unfortunately prevalent in relatively thin SiO
2
layers. For example, a thin SiO
2
layer often contains pinholes and/or localized voids due to unevenness at which the SiO
2
layer grows on a less than perfect silicon lattice or is deposited on the nitride layer. Additionally, the deposition of thin SiO
2
layers is more difficult to control due to inherent limitations of the deposition process.
Still another disadvantage is due to the penetration of impurities from a control gate (e.g., boron) into the top SiO
2
layer. This penetration of impurities causes a number of problems not only with the quality of the dielectric, but with the device operation. For example, boron penetration shifts a threshold voltage of a MOS device to a more positive value. Also, correlated with boron penetration is the degradation of a device's transconductance and the subthreshold slope.
Therefore, there exists a strong need in the art for an intergate dielectric layer which incorporates high-K dielectric material layers in place of the layers in a conventional ONO layer in order for semiconductor devices to be further scaled without reducing the data retention of the finished device.
SUMMARY OF THE INVENTION
One promising approach for maintaining the capacitance and thickness of the intergate dielectric layer may be to increase the permittivity of the layers in order to “reduce” an electrical equivalent thickness of the layer(s) of the intergate dielectric layer. Permittivity, ∈, of a material reflects the ability of the material to be polarized by an electric field. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, ∈
0
. Hence, the relative permittivity, referred to as the dielectric constant, of a material is defined as:
K
=∈/∈
0
While SiO
2
(sometimes simply referred to as “oxide”) has a dielectric constant of approximately 3.9, other materials have higher K values. Silicon nitride (“nitride”), for example, has a K of about 6 to 9 (depending on formation conditions) and aluminum oxide (Al
2
O
3
) has a K of about 9 to 10. Much higher K values of, for example, 20 or more can be obtained with various transition metal oxides including tantalum oxide (Ta
2
O
5
), barium strontium titanate (“BST”), and lead zirconate titanate (“PZT”).
For example, using a dielectric material with a higher K for one or more

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