Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-05-11
2009-08-11
Thai, Tuan V. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S118000, C711S154000
Reexamination Certificate
active
07574564
ABSTRACT:
A set associative cache includes a plurality of sets, where each set has a plurality of ways. The set associative cache has a plurality of replacement pointers where each set of the plurality of sets has a corresponding replacement pointer within the plurality of replacement pointers, and the corresponding replacement pointer indicates a way of the set. A cache command is provided which specifies a set of the plurality of sets and which specifies a replacement way value. In response to the cache command, a current way value of the replacement pointer corresponding to the specified set is replaced with the replacement way value. The cache may further include way locking control circuitry which indicates whether or not one or more ways is locked. By indicating a locked way with the replacement way value, a locked way can be overridden and thus be used for a subsequent cache line fill.
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Chiu Joanna G.
Freescale Semiconductor Inc.
King Robert L.
Thai Tuan V.
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